Datasheet

© 2009 Microchip Technology Inc. DS39632E-page 241
PIC18F2455/2550/4455/4550
TABLE 19-4: REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1
SPPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
PIR2
OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
TRISC TRISC7 TRISC6
— — — TRISC2 TRISC1 TRISC0 56
TRISD
(1)
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 56
SSPBUF MSSP Receive Buffer/Transmit Register 54
SSPADD MSSP Address Register in I
2
C Slave mode.
MSSP Baud Rate Reload Register in I
2
C Master mode.
54
TMR2 Timer2 Register 54
PR2 Timer2 Period Register 54
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 54
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 54
SSPSTAT SMP CKE D/A
PSR/WUA BF 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in I
2
C™ mode.
Note 1: These registers or bits are not implemented in 28-pin devices.