Datasheet

PIC18F2455/2550/4455/4550
DS39632E-page 228 © 2009 Microchip Technology Inc.
19.4.7 BAUD RATE
In I
2
C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower seven bits of the
SSPADD register (Figure 19-19). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
CY) on the
Q2 and Q4 clocks. In I
2
C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK
), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 19-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD. SSPADD values of less than 2 are not
supported. Due to the need to support I
2
C clock
stretching capability, I
2
C baud rates are partially
dependent upon system parameters, such as line
capacitance and pull-up strength. The parameters
provided in Table 19-3 are guidelines, and the actual
baud rate may be slightly slower than that predicted in
the table. The baud rate formula shown in the bit
description of Register 19-4 sets the maximum baud
rate that can occur for a given SSPADD value.
FIGURE 19-19: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 19-3: I
2
C™ CLOCK RATE W/BRG
SSPM3:SSPM0
BRG Down Counter
CLKO
F
OSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
FCY FCY * 2 BRG Value
F
SCL
(2 Rollovers of BRG)
10 MHz 20 MHz 18h 400 kHz
(1)
10 MHz 20 MHz 1Fh 312.5 kHz
10 MHz 20 MHz 63h 100 kHz
4 MHz 8 MHz 09h 400 kHz
(1)
4 MHz 8 MHz 0Ch 308 kHz
4 MHz 8 MHz 27h 100 kHz
1 MHz 2 MHz 02h 333 kHz
(1)
1 MHz 2 MHz 09h 100 kHz
Note 1: The I
2
C™ interface does not conform to the 400 kHz I
2
C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.