Datasheet

PIC18F2455/2550/4455/4550
DS39632E-page 20 © 2009 Microchip Technology Inc.
PORTD is a bidirectional I/O port or a Streaming
Parallel Port (SPP). These pins have TTL input buffers
when the SPP module is enabled.
RD0/SPP0
RD0
SPP0
19 38 38
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD1/SPP1
RD1
SPP1
20 39 39
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD2/SPP2
RD2
SPP2
21 40 40
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD3/SPP3
RD3
SPP3
22 41 41
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD4/SPP4
RD4
SPP4
27 2 2
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD5/SPP5/P1B
RD5
SPP5
P1B
28 3 3
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel B.
RD6/SPP6/P1C
RD6
SPP6
P1C
29 4 4
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel C.
RD7/SPP7/P1D
RD7
SPP7
P1D
30 5 5
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel D.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG
Configuration bit is cleared.