Datasheet

PIC18F2455/2550/4455/4550
DS39632E-page 196 © 2009 Microchip Technology Inc.
TABLE 18-1: REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
SPPCON
(3)
— — — — — — SPPOWN SPPEN 57
SPPCFG
(3)
CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 57
SPPEPS
(3)
RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0 57
SPPDATA
(3)
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 57
PIR1 SPPIF
(3)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE
(3)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP
(3)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
PORTE RDPU
(3)
— — — RE3
(1,2)
RE2
(3)
RE1
(3)
RE0
(3)
56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Streaming Parallel Port.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers and/or bits are unimplemented on 28-pin devices.