Datasheet

© 2009 Microchip Technology Inc. DS39632E-page 117
PIC18F2455/2550/4455/4550
TABLE 10-3: PORTB I/O SUMMARY
Pin Function
TRIS
Setting
I/O I/O Type Description
RB0/AN12/
INT0/FLT0/
SDI/SDA
RB0 0 OUT DIG LATB<0> data output; not affected by analog input.
1 IN TTL PORTB<0> data input; weak pull-up when RBPU
bit is cleared.
Disabled when analog input enabled.
(1)
AN12 1 IN ANA A/D Input Channel 12.
(1)
INT0 1 IN ST External Interrupt 0 input.
FLT0 1 IN ST Enhanced PWM Fault input (ECCP1 module); enabled in software.
SDI 1 IN ST SPI data input (MSSP module).
SDA 1 OUT DIG I
2
C™ data output (MSSP module); takes priority over port data.
1 IN I
2
C/SMB I
2
C data input (MSSP module); input type depends on module setting.
RB1/AN10/
INT1/SCK/
SCL
RB1 0 OUT DIG LATB<1> data output; not affected by analog input.
1 IN TTL PORTB<1> data input; weak pull-up when RBPU
bit is cleared.
Disabled when analog input enabled.
(1)
AN10 1 IN ANA A/D Input Channel 10.
(1)
INT1 1 IN ST External Interrupt 1 input.
SCK 0 OUT DIG SPI clock output (MSSP module); takes priority over port data.
1 IN ST SPI clock input (MSSP module).
SCL 0 OUT DIG I
2
C clock output (MSSP module); takes priority over port data.
1 IN I
2
C/SMB I
2
C clock input (MSSP module); input type depends on module setting.
RB2/AN8/
INT2/VMO
RB2 0 OUT DIG LATB<2> data output; not affected by analog input.
1 IN TTL PORTB<2> data input; weak pull-up when RBPU
bit is cleared.
Disabled when analog input enabled.
(1)
AN8 1 IN ANA A/D input channel 8.
(1)
INT2 1 IN ST External Interrupt 2 input.
VMO 0 OUT DIG External USB transceiver VMO data output.
RB3/AN9/
CCP2/VPO
RB3 0 OUT DIG LATB<3> data output; not affected by analog input.
1 IN TTL PORTB<3> data input; weak pull-up when RBPU
bit is cleared.
Disabled when analog input enabled.
(1)
AN9 1 IN ANA A/D Input Channel 9.
(1)
CCP2
(2)
0 OUT DIG CCP2 compare and PWM output.
1 IN ST CCP2 capture input.
VPO 0 OUT DIG External USB transceiver VPO data output.
RB4/AN11/
KBI0/CSSPP
RB4 0 OUT DIG LATB<4> data output; not affected by analog input.
1 IN TTL PORTB<4> data input; weak pull-up when RBPU
bit is cleared.
Disabled when analog input enabled.
(1)
AN11 1 IN ANA A/D Input Channel 11.
(1)
KBI0 1 IN TTL Interrupt-on-pin change.
CSSPP
(4)
0 OUT DIG SPP chip select control output.
RB5/KBI1/
PGM
RB5 0 OUT DIG LATB<5> data output.
1 IN TTL PORTB<5> data input; weak pull-up when RBPU
bit is cleared.
KBI1 1 IN TTL Interrupt-on-pin change.
PGM x IN ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
I
2
C/SMB = I
2
C/SMBus input buffer, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is
overridden for this option)
Note 1: Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when
PBADEN is set and digital inputs when PBADEN is cleared.
2: Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1.
3: All other pin functions are disabled when ICSP™ or ICD operation is enabled.
4: 40/44-pin devices only.