Datasheet

© 2009 Microchip Technology Inc. DS39755C-page 31
PIC18F2423/2523/4423/4523
2.2 Selecting and Configuring
Acquisition Time
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option of having an
automatically determined acquisition time.
Acquisition time may be set with the ACQT<2:0> bits
(ADCON2<5:3>), which provide a range of 2 to 20 T
AD.
When the GO/DONE
bit is set, the A/D module con-
tinues to sample the input for the selected acquisition
time, then automatically begins a conversion. Since the
acquisition time is programmed, there may be no need
to wait for an acquisition time between selecting a
channel and setting the GO/DONE
bit.
Manual acquisition time is selected when
ACQT<2:0> = 000. When the GO/DONE
bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE
bit. This option is
also the default Reset state of the ACQT<2:0> bits and
is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE
bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
2.3 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 13 T
AD per 12-bit conversion.
The source of the A/D conversion clock is software
selectable.
There are seven possible options for T
AD:
For correct A/D conversions, the A/D conversion clock
(T
AD) must be as short as possible, but greater than the
minimum T
AD. (For more information, see parameter 130
on page 41.)
Table 2-2 shows the resultant T
AD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 2-2: TAD vs. DEVICE OPERATING FREQUENCIES
•2 TOSC 32 TOSC
•4 TOSC 64 TOSC
•8 TOSC Internal RC Oscillator
•16 T
OSC
A/D Clock Source (TAD)
Assumes T
AD Min. = 0.8 μs
Operation ADCS<2:0> Maximum F
OSC
2 TOSC 000 2.50 MHz
4 TOSC 100 5.00 MHz
8 T
OSC 001 10.00 MHz
16 TOSC 101 20.00 MHz
32 T
OSC 010 40.00 MHz
64 T
OSC 110 40.00 MHz
RC
(2)
x11 1.00 MHz
(1)
Note 1: The RC source has a typical TAD time of 2.5 μs.
2: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a F
OSC
divider should be used instead; otherwise, the A/D accuracy specification may not be met.