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PIC18F2423/2523/4423/4523

Data Sheet

28/40/44-Pin, Enhanced Flash

Microcontrollers with 12-Bit A/D

and nanoWatt Technology

Summary of content (54 pages)

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PIC18F2423/2523/4423/4523 Data Sheet 28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology © 2009 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC18F2423/2523/4423/4523 28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology Power Management Features: Peripheral Highlights (Continued): • • • • • • • • • • • Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all four modes) and I2C™ Master and Slave modes • Enhanced USART module: - Support for RS-485, RS-232 and LIN/J2602 - RS-232 operation using internal oscillator block (no external crystal required) - Auto-wake-up on Start bit - Auto-Baud Detect
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PIC18F2423/2523/4423/4523 Pin Diagrams 28-Pin PDIP, SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC18F2423 PIC18F2523 MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT VSS OSC1/CLKI(3)/RA7 OSC2/CLKO(3)/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(2) RC2/CCP1 RC3/SCK/SCL RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3/AN9/CCP2(2) RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA 28 27 26 25 24 23 22 21 20 19 18 17
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PIC18F2423/2523/4423/4523 Pin Diagrams (Continued) 40-Pin PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PIC18F4423 PIC18F4523 MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKI(2)/RA7 OSC2/CLKO(2)/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3
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PIC18F2423/2523/4423/4523 Pin Diagrams (Continued) PIC18F4423 PIC18F4523 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 OSC2/CLKO(3)/RA6 OSC1/CLKI(3)/RA7 VSS VSS VDD VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT RB3/AN9/CCP2(2) NC RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD VDD RB0/INT0/FLT0/
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PIC18F2423/2523/4423/4523 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 25 3.0 Special Features of the CPU.....................................................................
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PIC18F2423/2523/4423/4523 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
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PIC18F2423/2523/4423/4523 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F2423 • PIC18LF2423 • PIC18F2523 • PIC18LF2523 • PIC18F4423 • PIC18LF4423 • PIC18F4523 • PIC18LF4523 Note: This data sheet documents only the devices’ features and specifications that are in addition to, or different from, the features and specifications of the PIC18F2420/2520/4420/4520 devices.
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PIC18F2423/2523/4423/4523 1.2 Other Special Features • 12-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, thereby reducing code overhead. • Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM.
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PIC18F2423/2523/4423/4523 TABLE 1-1: DEVICE FEATURES Features Operating Frequency PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523 DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 16,384 32,768 16,384 32,768 Program Memory (Instructions) 8,192 16,384 8,192 16,384 Data Memory (Bytes) 768 1,536 768 1,536 Data EEPROM Memory (Bytes) 256 256 256 256 Interrupt Sources 19 19 20 20 Ports A, B, C, D, E I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B,
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PIC18F2423/2523/4423/4523 FIGURE 1-1: PIC18F2423/2523 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Latch 8 8 inc/dec logic 20 Address Latch PCU PCH PCL Program Counter 31 Level Stack 12 Data Address<12> 4 BSR Address Latch Program Memory (16/32 Kbytes) RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT OSC2/CLKO(3)/RA6 OSC1/CLKI(3)/RA7 Data Memory ( 3.
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PIC18F2423/2523/4423/4523 FIGURE 1-2: PIC18F4423/4523 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Memory ( 3.
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PIC18F2423/2523/4423/4523 TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RE3 MCLR Pin Number Pin Buffer PDIP, Type Type QFN SOIC 1 26 VPP RE3 OSC1/CLKI/RA7 OSC1 9 6 I ST P I ST ST O — CLKO O — RA6 I/O TTL RA7 OSC2/CLKO/RA6 OSC2 10 Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input.
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PIC18F2423/2523/4423/4523 TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer PDIP, Type Type QFN SOIC Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI/C1OUT RA4 T0CKI C1OUT 6 RA5/AN4/SS/HLVDIN/ C2OUT RA5 AN4 SS HLVDIN C2OUT 7 27 I/O TTL I Analog Digital I/O. Analog Input 0. I/O TTL I Analog Digital I/O. Analog Input 1.
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PIC18F2423/2523/4423/4523 TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer PDIP, Type Type QFN SOIC Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
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PIC18F2423/2523/4423/4523 TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer PDIP, Type Type QFN SOIC Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 11 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) 12 RC2/CCP1 RC2 CCP1 13 RC3/SCK/SCL RC3 SCK SCL 14 RC4/SDI/SDA RC4 SDI SDA 15 RC5/SDO RC5 SDO 16 RC6/TX/CK RC6 TX CK 17 RC7/RX/DT RC7 RX DT 18 RE3 — VSS VDD 8 I/O O I Digital I/O. Timer1 oscillator output.
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PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RE3 MCLR Pin Number PDIP 1 Pin Buffer QFN TQFP Type Type 18 18 VPP RE3 OSC1/CLKI/RA7 OSC1 13 32 I ST P I ST 30 I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 14 33 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input.
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PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP Pin Buffer QFN TQFP Type Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI/C1OUT RA4 T0CKI C1OUT 6 RA5/AN4/SS/HLVDIN/ C2OUT RA5 AN4 SS HLVDIN C2OUT 7 19 20 21 22 23 24 19 I/O I TTL Analog Digital I/O. Analog Input 0. I/O I TTL Analog Digital I/O.
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PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP Pin Buffer QFN TQFP Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
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PIC18F2423/2523/4423/4523 TABLE 1-3: PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number PDIP Pin Buffer QFN TQFP Type Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 15 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) 16 RC2/CCP1/P1A RC2 CCP1 P1A 17 RC3/SCK/SCL RC3 SCK 18 34 35 36 37 32 23 RC5/SDO RC5 SDO 24 RC6/TX/CK RC6 TX CK 25 RC7/RX/DT RC7 RX DT 26 42 43 44 1 ST — ST Digital I/O. Timer1 oscillator output.
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PIC18F2423/2523/4423/4523 TABLE 1-3: Pin Name PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP Pin Buffer QFN TQFP Type Type Description PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when the PSP module is enabled.
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PIC18F2423/2523/4423/4523 TABLE 1-3: Pin Name PIC18F4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP Pin Buffer QFN TQFP Type Type Description PORTE is a bidirectional I/O port. RE0/RD/AN5 RE0 RD 8 25 25 AN5 RE1/WR/AN6 RE1 WR 9 26 10 27 — I Analog I/O I ST TTL I Analog I/O I ST TTL I Analog Digital I/O. Read control for Parallel Slave Port (see also WR and CS pins). Analog Input 5. Digital I/O. Write control for Parallel Slave Port (see CS and RD pins). Analog Input 6.
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PIC18F2423/2523/4423/4523 2.0 12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 10 inputs for the PIC18F2423/2523 devices and 13 for the PIC18F4423/4523 devices. This module allows conversion of an analog input signal to a corresponding 12-bit digital number.
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PIC18F2423/2523/4423/4523 REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W(1) R/W(1) R/W(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared AN2 AN1 AN0 0111(1) 1000 1001 1010 1011 1100 1101 1110 1111 AN3 0000(1) 0001 0010 0011 0100 0101 0110 AN4 PCFG<3:0> AN5(2) PCFG<3:0>: A/D Port Configuration Control bits:
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PIC18F2423/2523/4423/4523 REGISTER 2-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TA
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PIC18F2423/2523/4423/4523 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF-/CVREF pins. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D Converter can be configured as an analog input or as a digital I/O.
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PIC18F2423/2523/4423/4523 Wait for the A/D conversion to complete by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt Read the A/D Result registers (ADRESH:ADRESL) and clear the ADIF bit, if required. For the next conversion, go to step 1 or step 2, as required. 6. 7. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts. After this acquisition time has elapsed, the A/D conversion can be started.
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PIC18F2423/2523/4423/4523 2.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 2-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor, CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
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PIC18F2423/2523/4423/4523 2.2 Selecting and Configuring Acquisition Time 2.3 Selecting the A/D Conversion Clock The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option of having an automatically determined acquisition time. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 13 TAD per 12-bit conversion. The source of the A/D conversion clock is software selectable.
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PIC18F2423/2523/4423/4523 2.4 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ADCS<2:0> bits in ADCON2 should be updated in accordance with the clock source to be used. The ACQT<2:0> bits do not need to be adjusted as the ADCS<2:0> bits adjust the TAD time for the new clock speed.
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PIC18F2423/2523/4423/4523 2.6 A/D Conversions After the A/D conversion is completed or aborted, a 2 TCY wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Figure 2-4 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins.
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PIC18F2423/2523/4423/4523 2.8 Use of the CCP2 Trigger An A/D conversion can be started by the Special Event Trigger of the CCP2 module. This requires that the CCP2M<3:0> bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion, and the Timer1 (or Timer3) counter will be reset to zero.
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PIC18F2423/2523/4423/4523 3.0 SPECIAL FEATURES OF THE CPU Note: 3.1 For additional details on the Configuration bits, refer to Section 23.1 “Configuration Bits” in the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631). Device ID information presented in this section is for the PIC18F2423/2523/4423/4523 devices only. TABLE 3-1: Device ID Registers The Device ID registers are read-only registers.
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PIC18F2423/2523/4423/4523 REGISTER 3-2: R DEV11 (1) DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2423/2523/4423/4523 R R R R R R R DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit -n = Value when device is unprogrammed bit 7-0 Note 1: U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state DEV<11:4>: Device ID bits(1) These bits are used with the DEV<3:0> bits in Device ID Register 1 to identify the part numbe
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PIC18F2423/2523/4423/4523 4.0 Note: ELECTRICAL CHARACTERISTICS Other than some basic data, this section documents only the PIC18F2423/2523/4423/4523 devices’ specifications that differ from those of the PIC18F2420/2520/4420/4520 devices. For detailed information on the electrical specifications shared by the PIC18F2423/2523/4423/4523 and PIC18F2420/2520/4420/4520 devices, see the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631). Absolute Maximum Ratings(†) Ambient temperature under bias...................
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PIC18F2423/2523/4423/4523 FIGURE 4-1: PIC18F2423/2523/4423/4523 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18F2423/2523/4423/4523 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 4-2: PIC18F2423/2523/4423/4523 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V Voltage 5.0V PIC18F2423/2523/4423/4523 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 25 MHz Frequency DS39755C-page 38 © 2009 Microchip Technology Inc.
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PIC18F2423/2523/4423/4523 FIGURE 4-3: PIC18LF2423/2523/4423/4523 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V 4.5V PIC18LF2423/2523/4423/4523 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. © 2009 Microchip Technology Inc.
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PIC18F2423/2523/4423/4523 TABLE 4-1: Param No. A/D CONVERTER CHARACTERISTICS: PIC18F2423/2523/4423/4523 (INDUSTRIAL) PIC18LF2423/2523/4423/4523 (INDUSTRIAL) Sym Characteristic Min Typ Max Units Conditions ΔVREF ≥ 3.0V A01 NR Resolution — — 12 bit A03 EIL Integral Linearity Error — <±1 ±2.0 LSB VDD = 3.0V ΔVREF ≥ 3.
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PIC18F2423/2523/4423/4523 FIGURE 4-4: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK(1) 132 11 A/D DATA 10 9 ... ... 3 2 1 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
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PIC18F2423/2523/4423/4523 5.0 PACKAGING INFORMATION For packaging information, see Section 28.0 “Packaging Information” in the “PIC18F2420/2520/4420/4520 Data Sheet” (DS39631). © 2009 Microchip Technology Inc.
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PIC18F2423/2523/4423/4523 APPENDIX A: REVISION HISTORY Revision A (June 2006) Original data sheet for PIC18F2423/2523/4423/4523 devices. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (January 2007) This revision includes updates to the packaging diagrams. Revision C (September 2009) Electrical specifications updated. Preliminary condition status removed. Converted document to the “mini data sheet” format.
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PIC18F2423/2523/4423/4523 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable DS39755C-page 46 APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a Baseline device (i.
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PIC18F2423/2523/4423/4523 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442”. The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations.
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INDEX A I A/D ...................................................................................... 25 A/D Converter Interrupt, Configuring .......................... 29 Acquisition Requirements ........................................... 30 ADCON0 Register....................................................... 25 ADCON1 Register....................................................... 25 ADCON2 Register....................................................... 25 ADRESH Register..............................
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PIC18F2423/2523/4423/4523 R T Reader Response ............................................................... 52 Registers ADCON0 (A/D Control 0) ............................................ 25 ADCON1 (A/D Control 1) ............................................ 26 ADCON2 (A/D Control 2) ............................................ 27 DEVID1 (Device ID 1) ................................................. 35 DEVID2 (Device ID 2) ....................................................... 36 Revision History ...
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PIC18F2423/2523/4423/4523 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC18F2423/2523/4423/4523 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC18F2423/2523/4423/4523 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F2423(1), PIC18F2523(1), PIC18F4423T(2), PIC18F4523T(2); VDD range 4.2V to 5.5V PIC18F2423(1), PIC18F2523(1), PIC18F4423T(2), PIC18F4523T(2); VDD range 2.0V to 5.
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