Datasheet

© 2006 Microchip Technology Inc. DS39564C-page 91
PIC18FXX2
FIGURE 9-5: BLOCK DIAGRAM OF RB2:RB0 PINS
FIGURE 9-6: BLOCK DIAGRAM OF RB3 PIN
Data Latch
RBPU
(2)
P
V
DD
QD
CK
QD
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
Weak
Pull-up
RD Port
RB0/INT
I/O pin
(1)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note 1: I/O pins have diode protection to V
DD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU
bit (OPTION_REG<7>).
Data Latch
P
V
DD
QD
CK
Q
D
EN
Data Bus
WR LATB or
WR TRISB
RD TRISB
RD PORTB
Weak
Pull-up
CCP2 Input
(3)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
RD LATB
WR PORTB
RBPU
(2)
CK
D
Enable
(3)
CCP Output
RD PORTB
CCP Output
(3)
1
0
P
N
V
DD
VSS
I/O pin
(1)
Q
CCP2MX
CCP2MX = 0
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU
bit (INTCON2<7>).
3: The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (=’0’) in the configuration register.