Datasheet

© 2006 Microchip Technology Inc. DS39564C-page 71
PIC18FXX2
7.0 8 X 8 HARDWARE MULTIPLIER
7.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX2 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 7-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 7-1: PERFORMANCE COMPARISON
7.2 Operation
Example 7-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 7-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 7-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
Example 7-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 7-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 7-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
Routine Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned
Without hardware multiply 13 69 6.9 μs27.6 μs69 μs
Hardware multiply 1 1 100 ns 400 ns 1 μs
8 x 8 signed
Without hardware multiply 33 91 9.1 μs36.4 μs91 μs
Hardware multiply 6 6 600 ns 2.4 μs6 μs
16 x 16 unsigned
Without hardware multiply 21 242 24.2 μs96.8 μs242 μs
Hardware multiply 24 24 2.4 μs9.6 μs24 μs
16 x 16 signed
Without hardware multiply 52 254 25.4 μs 102.6 μs254 μs
Hardware multiply 36 36 3.6 μs14.4 μs36 μs
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 2
16
) +
(ARG1H • ARG2L • 2
8
) +
(ARG1L • ARG2H • 2
8
) +
(ARG1L • ARG2L)