Datasheet

© 2006 Microchip Technology Inc. DS39564C-page 47
PIC18FXX2
OSCCON — — — — — — —SCS---- ---0 21
LVDCON
— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 191
WDTCON
— — — — — — —SWDTE---- ---0 203
RCON IPEN
— —RITO PD POR BOR 0--1 11qq 53, 28, 84
TMR1H Timer1 Register High Byte xxxx xxxx 107
TMR1L Timer1 Register Low Byte xxxx xxxx 107
T1CON RD16
— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 107
TMR2 Timer2 Register 0000 0000 111
PR2 Timer2 Period Register 1111 1111 112
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 111
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 125
SSPADD SSP Address Register in I
2
C Slave mode. SSP Baud Rate Reload Register in I
2
C Master mode. 0000 0000 134
SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 126
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 127
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 137
ADRESH A/D Result Register High Byte xxxx xxxx 187,188
ADRESL A/D Result Register Low Byte xxxx xxxx 187,188
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
—ADON0000 00-0 181
ADCON1 ADFM ADCS2
— — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 182
CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx 121, 123
CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx 121, 123
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 117
CCPR2H Capture/Compare/PWM Register2 High Byte xxxx xxxx 121, 123
CCPR2L Capture/Compare/PWM Register2 Low Byte xxxx xxxx 121, 123
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 117
TMR3H Timer3 Register High Byte xxxx xxxx 113
TMR3L Timer3 Register Low Byte xxxx xxxx 113
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 0000 0000 113
SPBRG USART1 Baud Rate Generator 0000 0000 168
RCREG USART1 Receive Register 0000 0000 175, 178,
180
TXREG USART1 Transmit Register 0000 0000 173, 176,
179
TXSTA CSRC TX9 TXEN SYNC
— BRGH TRMT TX9D 0000 -010 166
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 167
EEADR Data EEPROM Address Register 0000 0000 65, 69
EEDATA Data EEPROM Data Register 0000 0000 69
EECON2 Data EEPROM Control Register 2 (not a physical register) ---- ---- 65, 69
EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD xx-0 x000 66
TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear.