Datasheet

© 2006 Microchip Technology Inc. DS39564C-page 287
PIC18FXX2
TABLE 22-21: A/D CONVERTER CHARACTERISTICS: PIC18FXX2 (INDUSTRIAL, EXTENDED)
PIC18LFXX2 (INDUSTRIAL)
FIGURE 22-22: A/D CONVERSION TIMING
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
A01 N
R Resolution — — 10 bit
A03 E
IL Integral linearity error — — <±1 LSb VREF = VDD = 5.0V
A04 EDL Differential linearity error — — <±1 LSb VREF = VDD = 5.0V
A05 E
G Gain error — — <±1 LSb VREF = VDD = 5.0V
A06 EOFF Offset error — — <±1.5 LSb VREF = VDD = 5.0V
A10
— Monotonicity guaranteed
(2)
—VSS ≤ VAIN ≤ VREF
A20
A20A
VREF Reference Voltage
(V
REFH – VREFL)
1.8V
3V
—
—
—
—
V
V
V
DD < 3.0V
V
DD ≥ 3.0V
A21 VREFH Reference voltage High AVSS —AVDD + 0.3V V
A22 V
REFL Reference voltage Low AVSS – 0.3V — VREFH V
A25 V
AIN Analog input voltage AVSS – 0.3V — AVDD + 0.3V V VDD ≥ 2.5V (Note 3)
A30 Z
AIN Recommended impedance of
analog voltage source
—— 2.5kΩ (Note 4)
A50 I
REF VREF input current (Note 1) —
—
—
—
5
150
μA
μA
During VAIN acquisition
During A/D conversion cycle
Note 1: Vss ≤ V
AIN ≤ VREF
2: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
3: For V
DD < 2.5V, VAIN should be limited to < .5 VDD.
4: Maximum allowed impedance for analog voltage source is 10 kΩ. This requires higher acquisition times.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 nS), which also disconnects the holding capacitor from the analog input.
. . .
. . .
TCY