Datasheet

PIC18FXX2
DS39564C-page 286 © 2006 Microchip Technology Inc.
FIGURE 22-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 22-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 22-21: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 22-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS
121
121
120
122
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 22-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid PIC18FXXX — 50 ns
PIC18LFXXX — 150 ns V
DD = 2V
121 Tckr Clock out rise time and fall time
(Master mode)
PIC18FXXX — 25 ns
PIC18LFXXX — 60 ns V
DD = 2V
122 Tdtr Data out rise time and fall time PIC18FXXX — 25 ns
PIC18LFXXX — 60 ns VDD = 2V
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 22-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data hold before CK ↓ (DT hold time) 10 — ns
126 TckL2dtl Data hold after CK ↓ (DT hold time) PIC18FXXX 15 — ns
PIC18LFXXX 20 — ns V
DD = 2V