Datasheet

© 2006 Microchip Technology Inc. DS39564C-page 285
PIC18FXX2
TABLE 22-18: MASTER SSP I
2
C BUS DATA REQUIREMENTS
Param.
No.
Symbol Characteristic Min Max Units Conditions
100 THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(T
OSC)(BRG + 1) — ms
1 MHz mode
(1)
2(TOSC)(BRG + 1) — ms
101 TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(T
OSC)(BRG + 1) — ms
1 MHz mode
(1)
2(TOSC)(BRG + 1) — ms
102 T
R SDA and SCL
rise time
100 kHz mode — 1000 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB 300 ns
1 MHz mode
(1)
— 300 ns
103 T
F SDA and SCL
fall time
100 kHz mode — 1000 ns VDD ≥ 4.2V
400 kHz mode 20 + 0.1 C
B 300 ns VDD ≥ 4.2V
90 TSU:STA START condition
setup time
100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for
Repeated START
condition
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode
(1)
2(TOSC)(BRG + 1) — ms
91 T
HD:STA START condition
hold time
100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first
clock pulse is generated
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode
(1)
2(TOSC)(BRG + 1) — ms
106 THD:DAT Data input
hold time
100 kHz mode 0 — ns
400 kHz mode 0 0.9 ms
107 T
SU:DAT Data input
setup time
100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 T
SU:STO STOP condition
setup time
100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode
(1)
2(TOSC)(BRG + 1) — ms
109 TAA Output valid from
clock
100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode
(1)
——ns
110 T
BUF Bus free time 100 kHz mode 4.7 — ms Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — ms
D102 C
B Bus capacitive loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I
2
C pins.
2: A Fast mode I
2
C bus device can be used in a Standard mode I
2
C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line
is released.