Datasheet

PIC18FXX2
DS39564C-page 284 © 2006 Microchip Technology Inc.
FIGURE 22-18: MASTER SSP I
2
C BUS START/STOP BITS TIMING WAVEFORMS
TABLE 22-17: MASTER SSP I
2
C BUS START/STOP BITS REQUIREMENTS
FIGURE 22-19: MASTER SSP I
2
C BUS DATA TIMING
Note: Refer to Figure 22-4 for load conditions.
91
93
SCL
SDA
START
Condition
STOP
Condition
90
92
Param.
No.
Symbol Characteristic Min Max Units Conditions
90
T
SU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for
Repeated START
condition
Setup time 400 kHz mode 2(T
OSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
91 T
HD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the
first clock pulse is
generated
Hold time 400 kHz mode 2(T
OSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
92 T
SU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Setup time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
93 T
HD:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Hold time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
Note 1: Maximum pin capacitance = 10 pF for all I
2
C pins.
Note: Refer to Figure 22-4 for load conditions.
90
91 92
100
101
103
106
107
109
109
110
102
SCL
SDA
In
SDA
Out