Datasheet

PIC18FXX2
DS39564C-page 280 © 2006 Microchip Technology Inc.
FIGURE 22-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
TABLE 22-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))
Param. No. Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
Ts sL 2scL
SS
↓ to SCK↓ or SCK↑ input TCY —ns
71 TscH SCK input high time (Slave mode) Continuous 1.25 T
CY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK input low time (Slave mode) Continuous 1.25 T
CY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge 100 — ns
73A T
B2B Last clock edge of Byte1 to the first clock edge of Byte2 1.5 TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge 100 — ns
75 TdoR SDO data output rise time PIC18FXXX — 25 ns
PIC18LFXXX — 60 ns
VDD = 2V
76 TdoF SDO data output fall time PIC18FXXX — 25 ns
PIC18LFXXX — 60 ns
VDD = 2V
77 TssH2doZ SS↑ to SDO output hi-impedance 10 50 ns
78 TscR SCK output rise time (Master mode) PIC18FXXX — 25 ns
PIC18LFXXX — 60 ns
VDD = 2V
79 TscF SCK output fall time (Master mode) PIC18FXXX — 25 ns
PIC18LFXXX — 60 ns
VDD = 2V
80 TscH2doV,
TscL2doV
SDO data output valid after SCK edge PIC18FXXX — 50 ns
PIC18LFXXX — 150 ns
VDD = 2V
83 TscH2ssH,
Ts cL 2ssH
SS ↑ after SCK edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
77
78
79
80
79
78
SDI
MSb LSb
bit6 - - - - - -1
MSb In bit6 - - - -1 LSb In
83
Note: Refer to Figure 22-4 for load conditions.