Datasheet

© 2006 Microchip Technology Inc. DS39564C-page 277
PIC18FXX2
FIGURE 22-11: PARALLEL SLAVE PORT TIMING (PIC18F4X2)
TABLE 22-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X2)
Note: Refer to Figure 22-4 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
Param.
No.
Symbol Characteristic Min Max Units Conditions
62 TdtV2wrH Data in valid before WR
↑ or CS↑
(setup time)
20
25
—
—
ns
ns Extended Temp. Range
63 TwrH2dtI WR↑ or CS↑ to data–in invalid
(hold time)
PIC18FXXX 20 — ns
PIC18LFXXX 35 — ns V
DD = 2V
64 TrdL2dtV RD
↓ and CS↓ to data–out valid —
—
80
90
ns
ns Extended Temp. Range
65 TrdH2dtI RD
↑ or CS↓ to data–out invalid 10 30 ns
66 TibfINH Inhibit of the IBF flag bit being cleared from
WR
↑ or CS↑
—3 T
CY