Datasheet

PIC18FXX2
DS39564C-page 274 © 2006 Microchip Technology Inc.
FIGURE 22-8: BROWN-OUT RESET TIMING
TABLE 22-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
VDD
BVDD
35
VBGAP = 1.2V
V
IRVST
Enable Internal Reference Voltage
Internal Reference Voltage stable
36
Typical
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 TmcL MCLR
Pulse Width (low) 2 — — μs
31 TWDT Watchdog Timer Time-out Period
(No Postscaler)
71833ms
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 TPWRT Power up Timer Period 28 72 132 ms
34 T
IOZ I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
—2—μs
35 T
BOR Brown-out Reset Pulse Width 200 — — μsVDD ≤ BVDD (see
D005)
36 T
IVRST Time for Internal Reference
Voltage to become stable
—20500μs
37 T
LVD Low Voltage Detect Pulse Width 200 — — μsVDD ≤ VLVD (see
D420)