Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PDIP 40 8-Bit 40 MHz I/O number 34

PIC18FXX2

If the main oscillator is configured for HS-PLL mode, an

oscillator start-up time (T

OST) plus an additional PLL

time-out (T

PLL) will occur. The PLL time-out is typically

2 ms and allows the PLL to lock to the main oscillator

frequency. A timing diagram indicating the transition

from the Timer1 oscillator to the main oscillator for

HS-PLL mode is shown in Figure 2-10.

FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)

If the main oscillator is configured in the RC, RCIO, EC

or ECIO modes, there is no oscillator start-up time-out.

Operation will resume after eight cycles of the main

oscillator have been counted. A timing diagram, indi-

cating the transition from the Timer1 oscillator to the

main oscillator for RC, RCIO, EC and ECIO modes, is

shown in Figure 2-11.

FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)

Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2

OSC1

Internal System

SCS

(OSCCON<0>)

Program Counter

PC PC + 2

Note 1: TOST = 1024 TOSC (drawing not to scale).

T1OSI

Clock

TOST

PC + 4

TPLL

TOSC

TT1P

TSCS

OSC2

PLL Clock

Input

1 234 5678

Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3