Datasheet

PIC18FXX2
DS39564C-page 182 © 2006 Microchip Technology Inc.
REGISTER 17-2: ADCON1 REGISTER
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ADCS2
— — PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.
bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)
bit 5-4 Unimplemented: Read as '0'
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: On any device RESET, the port pins that are multiplexed with analog functions (ANx) are
forced to be an analog input.
ADCON1
<ADCS2>
ADCON0
<ADCS1:ADCS0>
Clock Conversion
0 00 FOSC/2
0 01 F
OSC/8
0 10 F
OSC/32
0 11 F
RC (clock derived from the internal A/D RC oscillator)
1 00 F
OSC/4
1 01 F
OSC/16
1 10 F
OSC/64
1 11 F
RC (clock derived from the internal A/D RC oscillator)
A = Analog input D = Digital I/O
C/R = # of analog input channels / # of A/D voltage references
PCFG
<3:0>
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 V
REF+VREF-C / R
0000 AAAA A A AAV
DD VSS 8 / 0
0001 AAAAV
REF+A AAAN3VSS 7 / 1
0010 DDDA A A AAV
DD VSS 5 / 0
0011 DDDAV
REF+A AAAN3VSS 4 / 1
0100 DDDD A D AAV
DD VSS 3 / 0
0101 DDDDV
REF+D A AAN3VSS 2 / 1
011x DDDD D D DD — —0 / 0
1000 AAAAV
REF+VREF-A A AN3AN26 / 2
1001 DDAA A A AAV
DD VSS 6 / 0
1010 DDAAV
REF+A AAAN3VSS 5 / 1
1011 DDAAV
REF+VREF-A A AN3AN24 / 2
1100 DDDAV
REF+VREF-A A AN3AN23 / 2
1101 DDDDV
REF+VREF-A A AN3AN22 / 2
1110 DDDD D D DAV
DD VSS 1 / 0
1111 DDDDV
REF+VREF-D A AN3AN21 / 2