Datasheet

© 2006 Microchip Technology Inc. DS39564C-page 151
PIC18FXX2
15.4.7 BAUD RATE GENERATOR
In I
2
C Master mode, the baud rate generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 15-17). When a write occurs
to SSPBUF, the baud rate generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
CY) on the
Q2 and Q4 clocks. In I
2
C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK
), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 15-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 15-17: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 15-3: I
2
C CLOCK RATE W/BRG
SSPM3:SSPM0
BRG Down Counter
CLKO
Fosc/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
FCY FCY*2 BRG Value
F
SCL
(2)
(2 Rollovers of BRG)
10 MHz 20 MHz 19h 400 kHz
(1)
10 MHz 20 MHz 20h 312.5 kHz
10 MHz 20 MHz 3Fh 100 kHz
4 MHz 8 MHz 0Ah 400 kHz
(1)
4 MHz 8 MHz 0Dh 308 kHz
4 MHz 8 MHz 28h 100 kHz
1 MHz 2 MHz 03h 333 kHz
(1)
1 MHz 2 MHz 0Ah 100kHz
1 MHz 2 MHz 00h 1 MHz
(1)
Note 1: The I
2
C interface does not conform to the 400 kHz I
2
C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2: Actual frequency will depend on bus conditions. Theoretically, bus conditions will add rise time and extend
low time of clock period, producing the effective frequency.