Datasheet

PIC18FXX2
DS39564C-page 114 © 2006 Microchip Technology Inc.
13.1 Timer3 Operation
Timer3 can operate in one of these modes:
•As a timer
• As a synchronous counter
• As an asynchronous counter
The Operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored, and the pins are read as ‘0’.
Timer3 also has an internal “RESET input”. This RESET
can be generated by the CCP module (Section 14.0).
FIGURE 13-1: TIMER3 BLOCK DIAGRAM
FIGURE 13-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
TMR3H TMR3L
T1OSC
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
SLEEP Input
T1OSCEN
Enable
Oscillator
(1)
TMR3IF
Overflow
Interrupt
F
OSC/4
Internal
Clock
TMR3ON
On/Off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
T1OSO/
T1OSI
Flag bit
(3)
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T13CKI
CLR
CCP Special Trigger
T3CCPx
Timer3
TMR3L
T1OSC
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
SLEEP Input
T1OSCEN
Enable
Oscillator
(1)
FOSC/4
Internal
Clock
TMR3ON
On/Off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
T1OSO/
T1OSI
TMR3
T13CKI
CLR
CCP Special Trigger
T3CCPx
To Timer1 Clock Input
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
High Byte
Data Bus<7:0>
8
TMR3H
8
8
8
Read TMR3L
Write TMR3L
Set TMR3IF Flag bit
on Overflow