PIC18FXX2 Data Sheet High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D © 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18FXX2 28/40-pin High Performance, Enhanced FLASH Microcontrollers with 10-Bit A/D High Performance RISC CPU: Peripheral Features (Continued): • C compiler optimized architecture/instruction set - Source code compatible with the PIC16 and PIC17 instruction sets • Linear program memory addressing to 32 Kbytes • Linear data memory addressing to 1.
PIC18FXX2 RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 MCLR/VPP NC RB7/PGD RB6/PGC RB5/PGM RB4 NC Pin Diagrams 6 5 4 3 2 1 44 43 42 41 40 PLCC RA4/T0CKI RA5/AN4/SS/LVDIN RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI NC PIC18F442 PIC18F452 28 27 26 25 24 23 22 21 20 19 8 7 8 9 10 11 12 13 14 15 16 171 39 38 37 36 35 34 33 32 31 30 29 RB3/CCP2* RB2/INT2 RB1/INT1 RB0/INT0 VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/
PIC18FXX2 Pin Diagrams (Cont.
PIC18FXX2 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 17 3.0 Reset ...........................................................................................
PIC18FXX2 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
PIC18FXX2 NOTES: DS39564C-page 6 © 2006 Microchip Technology Inc.
PIC18FXX2 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F242 • PIC18F442 • PIC18F252 • PIC18F452 The following two figures are device block diagrams sorted by pin count: 28-pin for Figure 1-1 and 40/44-pin for Figure 1-2. The 28-pin and 40/44-pin pinouts are listed in Table 1-2 and Table 1-3, respectively. These devices come in 28-pin and 40/44-pin packages.
PIC18FXX2 FIGURE 1-1: PIC18F2X2 BLOCK DIAGRAM Data Bus<8> 21 Table Pointer 8 21 PORTA Data Latch 8 8 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN RA6 Data RAM inc/dec logic Address Latch 21 Address Latch Program Memory (up to 2 Mbytes) PCLATU PCLATH PCU PCH PCL Program Counter Data Latch 12 Address<12> 12 4 BSR 31 Level Stack 16 (2) Decode Table Latch 4 Bank0, F FSR0 FSR1 FSR2 12 inc/dec logic PORTB 8 ROM Latch RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2(1) RB4
PIC18FXX2 FIGURE 1-2: PIC18F4X2 BLOCK DIAGRAM Data Bus<8> PORTA 21 8 21 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN RA6 Data Latch Table Pointer 8 Data RAM (up to 4K address reach) 8 inc/dec logic Address Latch Address Latch 21 Program Memory (up to 2 Mbytes) (2) PCLATU PCLATH PCU PCH PCL Program Counter Data Latch 12 Address<12> PORTB 4 12 4 BSR FSR0 FSR1 FSR2 Bank0, F 31 Level Stack 16 Decode Table Latch RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2(1) RB4 RB5/PGM
PIC18FXX2 TABLE 1-2: PIC18F2X2 PINOUT I/O DESCRIPTIONS Pin Number Pin Name DIP MCLR/VPP 1 Pin Type SOIC Buffer Type 1 MCLR I ST VPP I ST — — NC — — OSC1/CLKI OSC1 9 9 I ST I CMOS O — CLKO O — RA6 I/O TTL CLKI OSC2/CLKO/RA6 OSC2 10 10 Description Master Clear (input) or high voltage ICSP programming enable pin. Master Clear (Reset) input. This pin is an active low RESET to the device. High voltage ICSP programming enable pin. These pins should be left unconnected.
PIC18FXX2 TABLE 1-2: PIC18F2X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP Pin Type SOIC Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 RB0 INT0 21 21 RB1/INT1 RB1 INT1 22 RB2/INT2 RB2 INT2 23 RB3/CCP2 RB3 CCP2 24 RB4 25 25 RB5/PGM RB5 PGM 26 26 RB6/PGC RB6 PGC 27 RB7/PGD RB7 PGD 28 I/O I TTL ST Digital I/O. External Interrupt 0. I/O I TTL ST External Interrupt 1.
PIC18FXX2 TABLE 1-2: PIC18F2X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP Pin Type SOIC Buffer Type Description PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 11 RC1/T1OSI/CCP2 RC1 T1OSI CCP2 12 RC2/CCP1 RC2 CCP1 13 RC3/SCK/SCL RC3 SCK SCL 14 RC4/SDI/SDA RC4 SDI SDA 15 RC5/SDO RC5 SDO 16 RC6/TX/CK RC6 TX CK 17 RC7/RX/DT RC7 RX DT 18 11 I/O O I ST — ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.
PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS Pin Number Pin Name DIP Pin Type PLCC TQFP 2 18 Description I ST Master Clear (input) or high voltage ICSP programming enable pin. Master Clear (Reset) input. This pin is an active low RESET to the device. High voltage ICSP programming enable pin. — — These pins should be left unconnected.
PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP Pin Type PLCC TQFP Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 RB0 INT0 33 36 RB1/INT1 RB1 INT1 34 RB2/INT2 RB2 INT2 35 RB3/CCP2 RB3 CCP2 36 RB4 37 41 14 RB5/PGM RB5 PGM 38 42 15 RB6/PGC RB6 PGC 39 RB7/PGD RB7 PGD 40 37 38 39 43 44 8 I/O I TTL ST Digital I/O. External Interrupt 0.
PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP Pin Type PLCC TQFP Buffer Type Description PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 15 RC1/T1OSI/CCP2 RC1 T1OSI CCP2 16 RC2/CCP1 RC2 CCP1 17 RC3/SCK/SCL RC3 SCK 18 16 18 19 20 32 23 RC5/SDO RC5 SDO 24 RC6/TX/CK RC6 TX CK 25 RC7/RX/DT RC7 RX DT 26 25 26 27 29 ST — ST I/O I I/O ST CMOS ST Digital I/O. Timer1 oscillator input.
PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP Pin Type PLCC TQFP Buffer Type Description PORTD is a bi-directional I/O port, or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled. RD0/PSP0 19 21 38 I/O ST TTL Digital I/O. Parallel Slave Port Data. RD1/PSP1 20 22 39 I/O ST TTL Digital I/O. Parallel Slave Port Data. RD2/PSP2 21 23 40 I/O ST TTL Digital I/O.
PIC18FXX2 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types TABLE 2-1: Ranges Tested: The PIC18FXX2 can be operated in eight different Oscillator modes. The user can program three configuration bits (FOSC2, FOSC1, and FOSC0) to select one of these eight modes: 1. 2. 3. 4. LP XT HS HS + PLL 5. 6. RC RCIO 7. 8. EC ECIO 2.
PIC18FXX2 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Ranges Tested: Mode Freq C1 C2 LP 32.0 kHz 33 pF 33 pF XT HS 200 kHz 15 pF 15 pF 200 kHz 22-68 pF 22-68 pF 1.0 MHz 15 pF 15 pF 4.0 MHz 15 pF 15 pF 4.0 MHz 15 pF 15 pF 8.0 MHz 15-33 pF 15-33 pF 20.0 MHz 15-33 pF 15-33 pF 25.0 MHz 15-33 pF 15-33 pF These values are for design guidance only. See notes following this table. 2.
PIC18FXX2 2.4 FIGURE 2-5: External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is no oscillator start-up time required after a Power-on Reset or after a recovery from SLEEP mode. 2.5 EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) HS/PLL The PLL can only be enabled when the oscillator configuration bits are programmed for HS mode.
PIC18FXX2 2.6 Oscillator Switching Feature The PIC18FXX2 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. For the PIC18FXX2 devices, this alternate clock source is the Timer1 oscillator. If a low frequency crystal (32 kHz, for example) has been attached to the Timer1 oscillator pins and the Timer1 oscillator has been enabled, the device can switch to a Low Power Execu- FIGURE 2-7: tion mode.
PIC18FXX2 2.6.1 SYSTEM CLOCK SWITCH BIT Note: The system clock source switching is performed under software control. The system clock switch bit, SCS (OSCCON<0>) controls the clock switching. When the SCS bit is ’0’, the system clock source comes from the main oscillator that is selected by the FOSC configuration bits in Configuration Register1H. When the SCS bit is set, the system clock source will come from the Timer1 oscillator. The SCS bit is cleared on all forms of RESET.
PIC18FXX2 2.6.2 OSCILLATOR TRANSITIONS A timing diagram indicating the transition from the main oscillator to the Timer1 oscillator is shown in Figure 2-8. The Timer1 oscillator is assumed to be running all the time. After the SCS bit is set, the processor is frozen at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are required after the synchronization cycles.
PIC18FXX2 If the main oscillator is configured for HS-PLL mode, an oscillator start-up time (TOST) plus an additional PLL time-out (TPLL) will occur. The PLL time-out is typically 2 ms and allows the PLL to lock to the main oscillator frequency. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS-PLL mode is shown in Figure 2-10.
PIC18FXX2 2.7 Effects of SLEEP Mode on the On-Chip Oscillator When the device executes a SLEEP instruction, the on-chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (Q1 state). With the oscillator off, the OSC1 and OSC2 signals will stop oscillating. Since all the transistor TABLE 2-3: switching currents have been removed, SLEEP mode achieves the lowest current consumption of the device (only leakage currents).
PIC18FXX2 3.0 RESET The PIC18FXXX differentiates between various kinds of RESET: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP Watchdog Timer (WDT) Reset (during normal operation) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 3-1. The Enhanced MCU devices have a MCLR noise filter in the MCLR Reset path.
PIC18FXX2 3.1 Power-On Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 3-2. When the device starts normal operation (i.e.
PIC18FXX2 TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) Oscillator Configuration Brown-out Wake-up from SLEEP or Oscillator Switch PWRTE = 0 PWRTE = 1 HS with PLL enabled(1) 72 ms + 1024 TOSC + 2ms 1024 TOSC + 2 ms 72 ms(2) + 1024 TOSC + 2 ms 1024 TOSC + 2 ms HS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms(2) + 1024 TOSC 1024 TOSC (2) — — EC 72 ms — 72 ms External RC 72 ms — 72 ms(2) Note 1: 2 ms is the nominal time required for the 4x PLL to lock.
PIC18FXX2 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TOSU 242 442 252 452 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3) TOSL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 242 442 252 452 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 242 442 252 452 ---0 0000 ---0 0000
PIC18FXX2 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt FSR1H 242 442 252 452 ---- xxxx ---- uuuu ---- uuuu FSR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu BSR 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu INDF2 242 442 252 452 N/A N/A N/A POSTINC2 242 442 252 452 N/A N/A N/A POSTDEC2 242 442 2
PIC18FXX2 TABLE 3-3: Register ADRESH INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices 242 442 Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt 252 452 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 242 442 252 452 0000 00-0 0000 00-0 uuuu uu-u ADCON1 242 442 252 452 00-- 0000 00-- 0000 uu-- uuuu CCPR1H 242 442 252 452 xxxx xxxx uuu
PIC18FXX2 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt IPR2 242 442 252 452 ---1 1111 ---1 1111 ---u uuuu PIR2 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu(1) PIE2 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu IPR1 PIR1 PIE1 242 442 252 452 1111 1111 1111 1111 uuuu uuuu 242 442 252 452 -111 1111 -111 1
PIC18FXX2 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 3-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 3-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39564C-page 32 © 2006 Microchip Technology Inc.
PIC18FXX2 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD) VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT TOST TPLL OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. © 2006 Microchip Technology Inc.
PIC18FXX2 NOTES: DS39564C-page 34 © 2006 Microchip Technology Inc.
PIC18FXX2 4.0 MEMORY ORGANIZATION There are three memory blocks in Enhanced MCU devices. These memory blocks are: • Program Memory • Data RAM • Data EEPROM Data and program memory use separate busses, which allows for concurrent access of these blocks. Additional detailed information for FLASH program memory and Data EEPROM is provided in Section 5.0 and Section 6.0, respectively. 4.1 Program Memory Organization A 21-bit program counter is capable of addressing the 2-Mbyte program memory space.
PIC18FXX2 FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F442/242 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR PIC18F452/252 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 • • • • • • Stack Level 31 Stack Level 31 RESET Vector 0000h RESET Vector 0000h High Priority Interrupt Vector 0008h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h Low Priority Interrupt Vector 0018h User Memory Space 3FFFh 4
PIC18FXX2 4.2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.
PIC18FXX2 REGISTER 4-1: STKPTR REGISTER R/C-0 STKOVF R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKUNF — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7(1) STKOVF: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6(1) STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as '0' bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 can only be cleared in user s
PIC18FXX2 4.3 Fast Register Stack 4.4 A “fast interrupt return” option is available for interrupts. A Fast Register Stack is provided for the STATUS, WREG and BSR registers and are only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the registers are then loaded back into the working registers, if the FAST RETURN instruction is used to return from the interrupt.
PIC18FXX2 4.6 Instruction Flow/Pipelining A fetch cycle begins with the program counter (PC) incrementing in Q1. An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18FXX2 4.7.1 TWO-WORD INSTRUCTIONS The PIC18FXX2 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to 1’s and is a special kind of NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed.
PIC18FXX2 4.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 4-6 and Figure 4-7 show the data memory organization for the PIC18FXX2 devices. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented.
PIC18FXX2 FIGURE 4-6: DATA MEMORY MAP FOR PIC18F242/442 BSR<3:0> = 0000 = 0001 = 0010 Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 000h 07Fh 080h 0FFh 100h GPR Bank 1 1FFh 200h FFh 00h Bank 2 GPR FFh 2FFh 300h Access Bank Access RAM low = 0011 = 1110 = 1111 Bank 3 to Bank 14 7Fh Access RAM high 80h (SFRs) FFh Unused Read ’00h’ 00h Unused FFh SFR Bank 15 00h EFFh F00h F7Fh F80h FFFh When a = 0, the BSR is ignored and the Access Bank is used.
PIC18FXX2 FIGURE 4-7: DATA MEMORY MAP FOR PIC18F252/452 BSR<3:0> = 0000 = 0001 = 0010 = 0011 Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 GPR Bank 1 FFh 00h Bank 2 1FFh 200h GPR 2FFh 300h FFh 00h Bank 3 GPR FFh = 0100 = 0101 Bank 4 3FFh 400h GPR = 1110 = 1111 Access Bank 4FFh 500h 00h GPR Bank 5 FFh = 0110 000h 07Fh 080h 0FFh 100h Bank 6 to Bank 14 5FFh 600h Unused Read ’00h’ 00h Unused FFh SFR Bank 15 EFFh F00h F7Fh F80h FFFh Access RAM low 00h 7Fh Access RAM high
PIC18FXX2 TABLE 4-1: Address FFFh FFEh SPECIAL FUNCTION REGISTER MAP Name TOSU TOSH Address Address Name FBFh CCPR1H F9Fh IPR1 FDEh POSTINC2(3) FBEh CCPR1L F9Eh PIR1 (3) FBDh CCP1CON F9Dh PIE1 FBCh CCPR2H F9Ch — FDFh Name INDF2 Address (3) FFDh TOSL FDDh FFCh STKPTR FDCh POSTDEC2 PREINC2(3) Name FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh — FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah — FF9h PCL FD9h FSR2L FB9h — F99h — FF8h TBLPTRU FD8h STATUS FB
PIC18FXX2 TABLE 4-2: File Name TOSU REGISTER FILE SUMMARY Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Top-of-Stack upper Byte (TOS<20:16>) Value on Details POR, BOR on page: ---0 0000 37 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 37 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 37 38 STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 PCLATU — — — Holding Register for PC<20:16> ---0 0000 39 PCLATH Holding Register for PC<15:8> 0000 0000 39 PCL PC
PIC18FXX2 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: OSCCON — — — — — — — SCS ---- ---0 LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 191 WDTCON — — — — — — — SWDTE ---- ---0 203 IPEN — — RI TO PD POR BOR File Name RCON 21 0--1 11qq 53, 28, 84 TMR1H Timer1 Register High Byte xxxx xxxx 107 TMR1L Timer1 Register Low Byte xxxx xxxx 107 TMR1ON 0-00 0000 1
PIC18FXX2 TABLE 4-2: File Name REGISTER FILE SUMMARY (CONTINUED) Value on Details POR, BOR on page: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 83 PIR2 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 79 PIE2 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 81 IPR1 PSPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 82 PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
PIC18FXX2 4.10 Access Bank 4.11 The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into sixteen banks. When using direct addressing, the BSR should be configured for the desired bank.
PIC18FXX2 4.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 4-9 shows the operation of indirect addressing.
PIC18FXX2 FIGURE 4-9: INDIRECT ADDRESSING OPERATION RAM 0h Instruction Executed Opcode Address FFFh 12 File Address = access of an indirect addressing register BSR<3:0> Instruction Fetched 4 Opcode FIGURE 4-10: 12 12 8 File FSR INDIRECT ADDRESSING Indirect Addressing 11 FSR Register 0 Location Select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table 4-1. © 2006 Microchip Technology Inc.
PIC18FXX2 4.13 STATUS Register The STATUS register, shown in Register 4-2, contains the arithmetic status of the ALU. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV, or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18FXX2 4.14 RCON Register Note 1: If the BOREN configuration bit is set (Brown-out Reset enabled), the BOR bit is ’1’ on a Power-on Reset. After a Brownout Reset has occurred, the BOR bit will be cleared, and must be set by firmware to indicate the occurrence of the next Brown-out Reset. The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device RESET. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable.
PIC18FXX2 NOTES: DS39564C-page 54 © 2006 Microchip Technology Inc.
PIC18FXX2 5.0 FLASH PROGRAM MEMORY 5.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: The FLASH Program Memory is readable, writable, and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time.
PIC18FXX2 FIGURE 5-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in Section 5.5. 5.
PIC18FXX2 REGISTER 5-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: FLASH Program or Data EEPROM Memory Select bit 1 = Access FLASH Program memory 0 = Access Data EEPROM memory bit 6 CFGS: FLASH Program/Data EE or Configuration Select bit 1 = Access Configuration registers 0 = Access FLASH Program or Data EEPROM memory bit 5 Unimplemented: Read as '0' bit 4 FREE: FLASH Row Erase Enable bit
PIC18FXX2 5.2.2 TABLAT - TABLE LATCH REGISTER 5.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. 5.2.3 TBLPTR is used in reads, writes, and erases of the FLASH program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program memory into TABLAT.
PIC18FXX2 5.3 Reading the FLASH Program Memory The TBLRD instruction is used to retrieve data from program memory and place into data RAM. Table Reads from program memory are performed one byte at a time. FIGURE 5-4: TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next Table Read operation. The internal program memory is typically organized by words.
PIC18FXX2 5.4 5.4.1 Erasing FLASH Program memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control can larger blocks of program memory be bulk erased. Word erase in the FLASH array is not supported. FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is: 1.
PIC18FXX2 5.5 Writing to FLASH Program Memory The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. Table Writes are used internally to load the holding registers needed to program the FLASH memory. There are 8 holding registers used by the Table Writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation.
PIC18FXX2 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; number of bytes in erase block ; point to buffer
PIC18FXX2 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF BCF BSF BCF MOVLW Required MOVWF Sequence MOVLW MOVWF BSF BSF DECFSZ BRA BCF 5.5.
PIC18FXX2 NOTES: DS39564C-page 64 © 2006 Microchip Technology Inc.
PIC18FXX2 6.0 DATA EEPROM MEMORY The Data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are four SFRs used to read and write the program and data EEPROM memory. These registers are: • • • • EECON1 EECON2 EEDATA EEADR The EEPROM data memory allows byte read and write.
PIC18FXX2 REGISTER 6-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: FLASH Program or Data EEPROM Memory Select bit 1 = Access FLASH Program memory 0 = Access Data EEPROM memory bit 6 CFGS: FLASH Program/Data EE or Configuration Select bit 1 = Access Configuration or Calibration registers 0 = Access FLASH Program or Data EEPROM memory bit 5 Unimplemented: Read as '0' bit 4 FREE: FLASH Row Er
PIC18FXX2 6.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>), clear the CFGS control bit EXAMPLE 6-1: MOVLW MOVWF BCF BCF BSF MOVF 6.4 DATA EEPROM READ DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, CFGS EECON1, RD EEDATA, W ; ; ; ; ; ; Data Memory Address to read Point to DATA memory Access program FLASH or Data EEPROM memory EEPROM Read W = EEDATA Writing to the Data EEPROM Memory cution (i.e.
PIC18FXX2 6.5 Write Verify 6.7 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.6 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in.
PIC18FXX2 TABLE 6-1: Address FF2h REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on All Other RESETS INTCON GIE/ GIEH PEIE/ GIEL T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u FA9h EEADR EEPROM Address Register 0000 0000 0000 0000 FA8h EEDATA EEPROM Data Register 0000 0000 0000 0000 FA7h EECON2 EEPROM Control Register2 (not a physical register) FA6h EECON1 FA2h FA1h FA0h Legend: — — xx-0 x
PIC18FXX2 NOTES: DS39564C-page 70 © 2006 Microchip Technology Inc.
PIC18FXX2 7.0 8 X 8 HARDWARE MULTIPLIER Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: 7.1 Introduction • Higher computational throughput • Reduces code size requirements for multiply algorithms An 8 x 8 hardware multiplier is included in the ALU of the PIC18FXX2 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result.
PIC18FXX2 EXAMPLE 7-3: MOVF MULWF 16 x 16 UNSIGNED MULTIPLY ROUTINE EXAMPLE 7-4: ARG1L, W ARG2L MOVFF MOVFF ; ARG1L * ARG2L -> ; PRODH:PRODL PRODH, RES1 ; PRODL, RES0 ; MOVF MULWF ARG1H, W ARG2H ; 16 x 16 SIGNED MULTIPLY ROUTINE MOVF MULWF ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, RES1, PRODH, RES2, WREG RES3, MOVF MULWF ARG1H, W ARG2L MOVF ADDWF
PIC18FXX2 8.0 INTERRUPTS The PIC18FXX2 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation.
PIC18FXX2 FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Wake-up if in SLEEP mode Interrupt to CPU Vector to location 0008h GIEH/GIE TMR1IF TMR1IE TMR1IP IPE IPEN XXXXIF XXXXIE XXXXIP GIEL/PEIE IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit
PIC18FXX2 8.1 INTCON Registers Note: The INTCON Registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 8-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18FXX2 REGISTER 8-2: INTCON2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0:External Interrupt0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on fall
PIC18FXX2 REGISTER 8-3: INTCON3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as '0' bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3
PIC18FXX2 8.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Flag Registers (PIR1, PIR2).
PIC18FXX2 REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF bit 7 bit 0 bit 7-5 Unimplemented: Read as '0' bit 4 EEIF: Data EEPROM/FLASH Write Operation Interrupt Flag bit 1 = The Write operation is complete (must be cleared in software) 0 = The Write operation is not complete, or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be clear
PIC18FXX2 8.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable Registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18FXX2 REGISTER 8-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE bit 7 bit 0 bit 7-5 Unimplemented: Read as '0' bit 4 EEIE: Data EEPROM/FLASH Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 LVDIE: Low Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable b
PIC18FXX2 8.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority Registers (IPR1, IPR2). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18FXX2 REGISTER 8-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP bit 7 bit 0 bit 7-5 Unimplemented: Read as '0' bit 4 EEIP: Data EEPROM/FLASH Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 LVDIP: Low Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TM
PIC18FXX2 8.5 RCON Register The RCON register contains the bit which is used to enable prioritized interrupts (IPEN).
PIC18FXX2 8.6 INT0 Interrupt 8.7 External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge triggered: either rising, if the corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit INTxF is set. This interrupt can be disabled by clearing the corresponding enable bit INTxE.
PIC18FXX2 NOTES: DS39564C-page 86 © 2006 Microchip Technology Inc.
PIC18FXX2 9.0 I/O PORTS Depending on the device selected, there are either five ports or three ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC18FXX2 FIGURE 9-2: BLOCK DIAGRAM OF RA4/T0CKI PIN FIGURE 9-3: BLOCK DIAGRAM OF RA6 PIN ECRA6 or RCRA6 Enable Data Bus RD LATA Data Bus RD LATA WR LATA or PORTA D Q CK Q N Data Latch WR TRISA D Q CK Q VSS I/O pin(1) WR LATA or PORTA Q CK Q VDD P Data Latch Schmitt Trigger Input Buffer TRIS Latch D WR TRISA D Q CK Q N I/O pin(1) VSS TRIS Latch RD TRISA Q TTL Input Buffer D RD TRISA ENEN RD PORTA ECRA6 or RCRA6 Enable Q D EN TMR0 Clock Input RD PORTA Note 1: I/O p
PIC18FXX2 TABLE 9-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2/VREF- bit2 TTL Input/output or analog input or VREF-. RA3/AN3/VREF+ bit3 TTL Input/output or analog input or VREF+. RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type.
PIC18FXX2 9.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped.
PIC18FXX2 FIGURE 9-5: BLOCK DIAGRAM OF RB2:RB0 PINS VDD RBPU(2) Weak P Pull-up Data Latch D Q Data Bus I/O pin(1) WR Port CK TRIS Latch D Q WR TRIS TTL Input Buffer CK RD TRIS Q D EN RD Port RB0/INT Schmitt Trigger Buffer Note 1: 2: RD Port I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
PIC18FXX2 TABLE 9-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT0 bit0 TTL/ST(1) Input/output pin or external interrupt input0. Internal software programmable weak pull-up. RB1/INT1 bit1 TTL/ST(1) Input/output pin or external interrupt input1. Internal software programmable weak pull-up. RB2/INT2 bit2 TTL/ST(1) Input/output pin or external interrupt input2. Internal software programmable weak pull-up.
PIC18FXX2 9.3 PORTC, TRISC and LATC Registers The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides. PORTC is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode).
PIC18FXX2 TABLE 9-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit1 ST Input/output port pin, Timer1 oscillator input, or Capture2 input/ Compare2 output/PWM output when CCP2MX configuration bit is set. RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output.
PIC18FXX2 9.4 PORTD, TRISD and LATD Registers FIGURE 9-8: PORTD BLOCK DIAGRAM IN I/O PORT MODE This section is applicable only to the PIC18F4X2 devices. PORTD is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e.
PIC18FXX2 TABLE 9-7: PORTD FUNCTIONS Name Bit# Buffer Type RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0. RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1. bit2 ST/TTL (1) Input/output port pin or parallel slave port bit2. bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3. RD4/PSP4 bit4 ST/TTL (1) Input/output port pin or parallel slave port bit4.
PIC18FXX2 9.5 PORTE, TRISE and LATE Registers FIGURE 9-9: PORTE BLOCK DIAGRAM IN I/O PORT MODE This section is only applicable to the PIC18F4X2 devices. PORTE is a 3-bit wide, bi-directional port. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e.
PIC18FXX2 REGISTER 9-1: TRISE REGISTER R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write
PIC18FXX2 TABLE 9-9: PORTE FUNCTIONS Name Bit# RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 bit0 bit1 bit2 Buffer Type Function ST/TTL(1) Input/output port pin or read control input in Parallel Slave Port mode or analog input: RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected). ST/TTL(1) Input/output port pin or write control input in Parallel Slave Port mode or analog input: WR 1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected).
PIC18FXX2 9.6 FIGURE 9-10: Parallel Slave Port PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) The Parallel Slave Port is implemented on the 40-pin devices only (PIC18F4X2). PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit, PSPMODE (TRISE<4>) is set. It is asynchronously readable and writable by the external world through RD control input pin, RE0/RD and WR control input pin, RE1/WR.
PIC18FXX2 FIGURE 9-12: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 9-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on POR, BOR Value on All Other RESETS Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu LATD LATD Data Output bits xxxx xxxx uuuu uuuu TRISD PORTD Data Direction bits 1111 1111 1111 1111 ---- -000 ---- -000 ---- -xxx ---- -uuu Name PORTD Bit 7 Bit 6 Bit 5 Bit 4 B
PIC18FXX2 NOTES: DS39564C-page 102 © 2006 Microchip Technology Inc.
PIC18FXX2 10.
PIC18FXX2 FIGURE 10-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 1 1 RA4/T0CKI pin Programmable Prescaler 0 Sync with Internal Clocks TMR0L (2 TCY delay) T0SE 3 PSA Set Interrupt Flag bit TMR0IF on Overflow T0PS2, T0PS1, T0PS0 T0CS Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
PIC18FXX2 10.1 Timer0 Operation 10.2.1 Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software control, (i.e., it can be changed “on-the-fly” during program execution). Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0L register is written, the increment is inhibited for the following two instruction cycles.
PIC18FXX2 NOTES: DS39564C-page 106 © 2006 Microchip Technology Inc.
PIC18FXX2 11.0 TIMER1 MODULE Figure 11-1 is a simplified block diagram of the Timer1 module. The Timer1 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers; TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • RESET from CCP module special event trigger REGISTER 11-1: Register 11-1 details the Timer1 control register.
PIC18FXX2 11.1 Timer1 Operation When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored, and the pins are read as ‘0’.
PIC18FXX2 11.2 Timer1 Oscillator 11.4 A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 11-1 shows the capacitor selection for the Timer1 oscillator.
PIC18FXX2 TABLE 11-2: Name REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Value on All Other RESETS Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u INTCON GIE/GIEH PEIE/GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
PIC18FXX2 12.0 TIMER2 MODULE 12.1 The Timer2 module timer has the following features: • • • • • • • 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift Timer2 has a control register shown in Register 12-1.
PIC18FXX2 12.2 Timer2 Interrupt 12.3 The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. FIGURE 12-1: Output of TMR2 The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module, which optionally uses it to generate the shift clock.
PIC18FXX2 13.0 TIMER3 MODULE Figure 13-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers; TMR3H and TMR3L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • RESET from CCP module trigger REGISTER 13-1: Register 13-1 shows the Timer3 control register.
PIC18FXX2 13.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer3 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs.
PIC18FXX2 13.2 Timer1 Oscillator 13.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a low power oscillator rated up to 200 KHz. See Section 11.0 for further details. 13.3 If the CCP module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3.
PIC18FXX2 NOTES: DS39564C-page 116 © 2006 Microchip Technology Inc.
PIC18FXX2 14.0 CAPTURE/COMPARE/PWM (CCP) MODULES Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit Capture register, as a 16-bit Compare register or as a PWM Master/Slave Duty Cycle register. Table 14-1 shows the timer resources of the CCP Module modes. REGISTER 14-1: The operation of CCP1 is identical to that of CCP2, with the exception of the special event trigger.
PIC18FXX2 14.1 CCP1 Module 14.2 Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. TABLE 14-1: Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable.
PIC18FXX2 14.3 14.3.3 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on pin RC2/CCP1. An event is defined as one of the following: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge 14.3.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: 14.3.
PIC18FXX2 14.4 14.4.2 Compare Mode Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. In Compare mode, the 16-bit CCPR1 (CCPR2) register value is constantly compared against either the TMR1 register pair value, or the TMR3 register pair value. When a match occurs, the RC2/CCP1 (RC1/CCP2) pin is: • • • • TIMER1/TIMER3 MODE SELECTION 14.4.
PIC18FXX2 TABLE 14-3: Name REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 Value on All Other RESETS Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u INTCON GIE/GIEH PEIE/GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2I
PIC18FXX2 14.5 14.5.1 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 14-3 shows a simplified block diagram of the CCP module in PWM mode.
PIC18FXX2 14.5.3 SETUP FOR PWM OPERATION 3. The following steps should be taken when configuring the CCP module for PWM operation: 4. 1. 2. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. TABLE 14-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 14-5: Name Make the CCP1 pin an output by clearing the TRISC<2> bit.
PIC18FXX2 NOTES: DS39564C-page 124 © 2006 Microchip Technology Inc.
PIC18FXX2 15.0 15.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC18FXX2 15.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • • • • MSSP Control Register1 (SSPCON1) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) MSSP Shift Register (SSPSR) - Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read only. The upper two bits of the SSPSTAT are read/write.
PIC18FXX2 REGISTER 15-2: SSPCON1: MSSP CONTROL REGISTER1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still hold
PIC18FXX2 15.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0>) and SSPSTAT<7:6>.
PIC18FXX2 15.3.3 ENABLING SPI I/O 15.3.4 To enable the serial port, SSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers, and then set the SSPEN bit. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed.
PIC18FXX2 15.3.5 MASTER MODE Figure 15-3, Figure 15-5, and Figure 15-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 15-2) is to broadcast data by the software protocol. • • • • In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to.
PIC18FXX2 15.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. longer driven, even if in the middle of a transmitted byte, and becomes a floating output.
PIC18FXX2 FIGURE 15-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit0 bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle after Q2↓ SSPSR to SSPBUF FIGURE 15-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit
PIC18FXX2 15.3.8 SLEEP OPERATION 15.3.10 In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from SLEEP. After the device returns to Normal mode, the module will continue to transmit/ receive data. Table 15-1 shows the compatibility between the standard SPI modes and the states the CKP and CKE control bits. TABLE 15-1: In Slave mode, the SPI transmit/receive shift register operates asynchronously to the device.
PIC18FXX2 15.4 I2C Mode 15.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on START and STOP bits in hardware to determine a free bus (multi-master function). The MSSP module implements the Standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC18FXX2 REGISTER 15-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Mast
PIC18FXX2 REGISTER 15-4: SSPCON1: MSSP CONTROL REGISTER1 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitt
PIC18FXX2 REGISTER 15-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slav
PIC18FXX2 15.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I 2C operation.
PIC18FXX2 15.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON1<6>) is set. An MSSP interrupt is generated for each data transfer byte.
DS39564C-page 140 CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus Master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
© 2006 Microchip Technology Inc.
DS39564C-page 142 2 1 4 1 5 0 7 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 A8 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON<6>) CKP 3 1 Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A2 A1 Cleared in so
© 2006 Microchip Technology Inc.
PIC18FXX2 15.4.4 CLOCK STRETCHING Both 7- and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 15.4.4.
PIC18FXX2 15.4.4.5 Clock Synchronization and the CKP bit If a user clears the CKP bit, the SCL output is forced to ‘0’. Setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. If the user attempts to drive SCL low, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set, and all other devices on the I2C bus have de-asserted SCL.
DS39564C-page 146 CKP SSPOV (SSPCON<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs 8
© 2006 Microchip Technology Inc. 2 1 UA (SSPSTAT<1>) SSPOV (SSPCON<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA, and UA will remain set.
PIC18FXX2 15.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the START condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices.
PIC18FXX2 15.4.6 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET or when the MSSP module is disabled.
PIC18FXX2 15.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated START condition. Since the Repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
PIC18FXX2 15.4.7 BAUD RATE GENERATOR In I2C Master mode, the baud rate generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 15-17). When a write occurs to SSPBUF, the baud rate generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC18FXX2 15.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated START/STOP condition, de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is FIGURE 15-18: sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC18FXX2 15.4.8 I2C MASTER MODE START CONDITION TIMING 15.4.8.1 If the user writes the SSPBUF when a START sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). To initiate a START condition, the user sets the START condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and starts its count.
PIC18FXX2 15.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode).
PIC18FXX2 15.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the buffer full flag bit, BF, and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106).
DS39564C-page 156 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 D7 1 SCL held low while CPU responds to SSPIF After START condition, SEN cleared by hardware SSPBUF written 1 ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine From SSP interrupt 2 D6 Transmitting Dat
© 2006 Microchip Technology Inc.
PIC18FXX2 15.4.12 ACKNOWLEDGE SEQUENCE TIMING 15.4.13 A STOP bit is asserted on the SDA pin at the end of a receive/transmit by setting the STOP sequence enable bit, PEN (SSPCON2<2>). At the end of a receive/transmit the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the baud rate generator is reloaded and counts down to 0.
PIC18FXX2 15.4.14 SLEEP OPERATION 15.4.17 While in SLEEP mode, the I2C module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from SLEEP (if the MSSP interrupt is enabled). 15.4.15 EFFECT OF A RESET A RESET disables the MSSP module and terminates the current transfer. 15.4.16 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free.
PIC18FXX2 15.4.17.1 Bus Collision During a START Condition During a START condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the START condition (Figure 15-26). SCL is sampled low before SDA is asserted low (Figure 15-27). b) During a START condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 15-28).
PIC18FXX2 FIGURE 15-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable START sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. set BCLIF SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC18FXX2 15.4.17.2 Bus Collision During a Repeated START Condition reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated START condition, a bus collision occurs if: a) b) If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs.
PIC18FXX2 15.4.17.3 Bus Collision During a STOP Condition The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data '0' (Figure 15-31).
PIC18FXX2 NOTES: DS39564C-page 164 © 2006 Microchip Technology Inc.
PIC18FXX2 16.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.
PIC18FXX2 REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 — bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: bit 4 R/W-0 B
PIC18FXX2 REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 SPEN bit 7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode - Master: 1 = Enables
PIC18FXX2 16.1 USART Baud Rate Generator (BRG) Example 16-1 shows the calculation of the baud rate error for the following conditions: The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored.
PIC18FXX2 TABLE 16-3: BAUD RATE (Kbps) BAUD RATES FOR SYNCHRONOUS MODE FOSC = 40 MHz SPBRG value (decimal) 33 MHz SPBRG value (decimal) 25 MHz SPBRG value (decimal) 20 MHz SPBRG value (decimal) KBAUD % ERROR KBAUD % ERROR KBAUD % ERROR KBAUD % ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - NA - - NA - - 19.2 NA - - NA - - NA - - NA - - 76.8 76.92 +0.
PIC18FXX2 TABLE 16-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 40 MHz KBAUD % ERROR SPBRG value (decimal) NA - - 1.2 NA - 2.4 NA - BAUD RATE (Kbps) 0.3 33 MHz KBAUD % ERROR SPBRG value (decimal) NA - - - NA - - 2.40 -0.07 25 MHz KBAUD % ERROR SPBRG value (decimal) NA - - - NA - - 214 2.40 -0.15 162 20 MHz KBAUD % ERROR SPBRG value (decimal) NA - - NA - - 2.40 +0.16 129 9.6 9.62 +0.16 64 9.55 -0.54 53 9.53 -0.76 40 9.47 -1.36 32 19.
PIC18FXX2 TABLE 16-5: BAUD RATE (Kbps) BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 40 MHz SPBRG value (decimal) 33 MHz SPBRG value (decimal) 25 MHz SPBRG value (decimal) 20 MHz SPBRG value (decimal) KBAUD % ERROR KBAUD % ERROR KBAUD % ERROR KBAUD % ERROR 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - 9.60 -0.07 214 9.59 -0.15 162 9.62 +0.16 129 19.2 19.23 +0.16 129 19.
PIC18FXX2 16.2 USART Asynchronous Mode flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE ( PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register.
PIC18FXX2 FIGURE 16-2: ASYNCHRONOUS TRANSMISSION Write to TXREG BRG Output (Shift Clock) Word 1 RC6/TX/CK (pin) START bit bit 0 bit 1 TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 16-3: bit 7/8 STOP bit Word 1 Word 1 Transmit Shift Reg ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG RC6/TX/CK (pin) TXIF bit (Interrupt Reg. Flag) START bit TRMT bit (Transmit Shift Reg.
PIC18FXX2 16.2.2 USART ASYNCHRONOUS RECEIVER 16.2.3 The receiver block diagram is shown in Figure 16-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. To set up an Asynchronous Reception: 1. Initialize the SPBRG register for the appropriate baud rate.
PIC18FXX2 FIGURE 16-5: ASYNCHRONOUS RECEPTION START bit bit0 RX (pin) bit1 bit7/8 STOP bit Rcv Shift Reg Rcv Buffer Reg START bit bit0 START bit bit7/8 STOP bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG bit7/8 STOP bit RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
PIC18FXX2 16.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively.
PIC18FXX2 FIGURE 16-6: SYNCHRONOUS TRANSMISSION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit 0 bit 1 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 2 bit 7 Word 1 bit 0 bit 1 Word 2 bit 7 RC6/TX/CK pin Write to TXREG Reg Write Word1 Write Word2 TXIF bit (Interrupt Flag) TRMT bit TRMT TXEN bit Note: '1' '1' Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.
PIC18FXX2 16.3.2 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. 2. 3.
PIC18FXX2 16.4 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 16.4.
PIC18FXX2 16.4.2 USART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode and bit SREN, which is a “don't care” in Slave mode. 2. 3. 4. 5. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP.
PIC18FXX2 17.0 COMPATIBLE 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has four registers. These registers are: • • • • The Analog-to-Digital (A/D) converter module has five inputs for the PIC18F2X2 devices and eight for the PIC18F4X2 devices. This module has the ADCON0 and ADCON1 register definitions that are compatible with the mid-range A/D module. The ADCON0 register, shown in Register 17-1, controls the operation of the A/D module.
PIC18FXX2 REGISTER 17-2: ADCON1 REGISTER R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’. 0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.
PIC18FXX2 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+ pin and RA2/AN2/VREF- pin. Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a voltage reference) or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion.
PIC18FXX2 The value that is in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ ADRESL registers will contain unknown data after a Power-on Reset. 5. OR After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 17.1.
PIC18FXX2 To calculate the minimum acquisition time, Equation 17-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution.
PIC18FXX2 17.2 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. The seven possible options for TAD are: • • • • • • • 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal A/D module RC oscillator (2-6 μs) For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 μs. 17.
PIC18FXX2 17.4 A/D Conversions (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2 TAD wait is required before the next acquisition is started. After this 2 TAD wait, acquisition on the selected channel is automatically started. The GO/DONE bit can then be set to start the conversion. Figure 17-3 shows the operation of the A/D converter after the GO bit has been set. Clearing the GO/DONE bit during a conversion will abort the current conversion.
PIC18FXX2 17.5 Use of the CCP2 Trigger (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the “special event trigger” sets the GO/DONE bit (starts a conversion). An A/D conversion can be started by the “special event trigger” of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set).
PIC18FXX2 18.0 LOW VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do “housekeeping tasks” before the device voltage exits the valid operating range. This can be done using the Low Voltage Detect module. This module is a software programmable circuitry, where a device voltage trip point can be specified.
PIC18FXX2 FIGURE 18-2: LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVDIN LVD Control Register 16 to 1 MUX VDD LVDIF + Internally Generated Reference Voltage 1.2V Typical LVDEN The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to 1111. In this state, the comparator input is multiplexed from the external input pin, FIGURE 18-3: – LVDIN (Figure 18-3).
PIC18FXX2 18.1 Control Register The Low Voltage Detect Control register controls the operation of the Low Voltage Detect circuitry.
PIC18FXX2 18.2 Operation Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked. After doing the check, the LVD module may be disabled. Each time that the LVD module is enabled, the circuitry requires some time to stabilize.
PIC18FXX2 18.2.1 REFERENCE VOLTAGE SET POINT The Internal Reference Voltage of the LVD module may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter 36.
PIC18FXX2 NOTES: DS39564C-page 194 © 2006 Microchip Technology Inc.
PIC18FXX2 19.0 SPECIAL FEATURES OF THE CPU There are several features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving Operating modes and offer code protection.
PIC18FXX2 TABLE 19-1: CONFIGURATION BITS AND DEVICE IDS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value — FOSC2 FOSC1 FOSC0 --1- -111 300001h CONFIG1H — — OSCSEN — 300002h CONFIG2L — — — — BORV1 BORV0 BOREN PWRTEN ---- 1111 300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111 300005h CONFIG3H — — — — — — — CCP2MX ---- ---1 300006h CONFIG4L DEBUG — — — — LVP — STVREN 1--- -1-1 300008h CONFIG5L
PIC18FXX2 REGISTER 19-2: CONFIGURATION REGISTER 2 LOW (CONFIG2L: BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BORV1 BORV0 BOREN PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.5V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.
PIC18FXX2 REGISTER 19-4: CONFIGURATION REGISTER 3 HIGH (CONFIG3H: BYTE ADDRESS 300005h) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 — — — — — — — CCP2MX bit 7 bit 0 bit 7-1 Unimplemented: Read as ‘0’ bit 0 CCP2MX: CCP2 Mux bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed REGISTER 19-5: U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state CONF
PIC18FXX2 REGISTER 19-6: CONFIGURATION REGISTER 5 LOW (CONFIG5L: BYTE ADDRESS 300008h) U-0 — U-0 — U-0 — U-0 — R/C-1 R/C-1 (1) (1) CP3 CP2 R/C-1 R/C-1 CP1 CP0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 (006000-007FFFh) not code protected 0 = Block 3 (006000-007FFFh) code protected bit 2 CP2: Code Protection bit(1) 1 = Block 2 (004000-005FFFh) not code protected 0 = Block 2 (004000-005FFFh) code protected bit 1 CP1: Code Protection bit
PIC18FXX2 REGISTER 19-8: CONFIGURATION REGISTER 6 LOW (CONFIG6L: BYTE ADDRESS 30000Ah) U-0 — U-0 — U-0 — U-0 — R/C-1 WRT3 (1) R/C-1 WRT2 (1) R/C-1 R/C-1 WRT1 WRT0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 (006000-007FFFh) not write protected 0 = Block 3 (006000-007FFFh) write protected bit 2 WRT2: Write Protection bit(1) 1 = Block 2 (004000-005FFFh) not write protected 0 = Block 2 (004000-005FFFh) write protected bit 1 WRT1: Write Pr
PIC18FXX2 REGISTER 19-10: CONFIGURATION REGISTER 7 LOW (CONFIG7L: BYTE ADDRESS 30000Ch) U-0 — U-0 — U-0 — U-0 — R/C-1 EBTR3 (1) R/C-1 EBTR2 (1) R/C-1 R/C-1 EBTR1 EBTR0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1) 1 = Block 3 (006000-007FFFh) not protected from Table Reads executed in other blocks 0 = Block 3 (006000-007FFFh) protected from Table Reads executed in other blocks bit 2 EBTR2: Table Read Protection bit(1) 1 = Block 2 (004000-005FFFh)
PIC18FXX2 REGISTER 19-12: DEVICE ID REGISTER 1 FOR PIC18FXX2 (DEVID1: BYTE ADDRESS 3FFFFEh) R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F252 001 = PIC18F452 100 = PIC18F242 101 = PIC18F442 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision.
PIC18FXX2 19.2 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/CLKO/ RA6 pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset).
PIC18FXX2 19.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of the device programming, by the value written to the CONFIG2H configuration register. FIGURE 19-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 8 8 - to - 1 MUX WDTEN Configuration bit WDTPS2:WDTPS0 SWDTEN bit WDT Time-out Note: TABLE 19-2: WDPS2:WDPS0 are bits in register CONFIG2H.
PIC18FXX2 19.3 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared, but keeps running, the PD bit (RCON<3>) is cleared, the TO (RCON<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low or hi-impedance).
PIC18FXX2 WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) FIGURE 19-2: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKO(4) INT pin INTF flag (INTCON<1>) Interrupt Latency(3) GIEH bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: PC PC+2 PC+4 PC+4 Inst(PC) = SLEEP Inst(PC + 2) Inst(PC + 4) Inst(PC - 1) SLEEP Inst(PC + 2) PC + 4 Dummy Cycle 0008h 000Ah Inst(0008h) Inst(000Ah) Dummy
PIC18FXX2 19.4 Program Verification and Code Protection Each of the five blocks has three code protection bits associated with them. They are: The overall structure of the code protection on the PIC18 FLASH devices differs significantly from other PICmicro devices. • Code Protect bit (CPn) • Write Protect bit (WRTn) • External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. One of these is a boot block of 512 bytes.
PIC18FXX2 19.4.1 PROGRAM MEMORY CODE PROTECTION The user memory may be read to or written from any location using the Table Read and Table Write instructions. The device ID may be read with Table Reads. The configuration registers may be read and written with the Table Read and Table Write instructions. outside of that block is not allowed to read, and will result in reading ‘0’s. Figures 19-4 through 19-6 illustrate Table Write and Table Read protection.
PIC18FXX2 FIGURE 19-5: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB,EBTRB = 11 0001FFh 000200h TBLPTR = 000FFF WRT0,EBTR0 = 10 001FFFh 002000h PC = 002FFE TBLRD * WRT1,EBTR1 = 11 003FFFh 004000h WRT2,EBTR2 = 11 005FFFh 006000h WRT3,EBTR3 = 11 007FFFh Results: All Table Reads from external blocks to Blockn are disabled whenever EBTRn = ‘0’. TABLAT register returns a value of “0”.
PIC18FXX2 19.4.2 DATA EEPROM CODE PROTECTION The entire Data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of Data EEPROM. WRTD inhibits external writes to Data EEPROM. The CPU can continue to read and write Data EEPROM regardless of the protection bit settings. 19.4.3 CONFIGURATION REGISTER PROTECTION The configuration registers can be write protected. The WRTC bit controls protection of the configuration registers.
PIC18FXX2 20.0 INSTRUCTION SET SUMMARY The PIC18FXXX instruction set adds many enhancements to the previous PICmicro instruction sets, while maintaining an easy migration from these PICmicro instruction sets. Most instructions are a single program memory word (16-bits), but there are three instructions that require two program memory locations.
PIC18FXX2 TABLE 20-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7) BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit; d = 0: store result in WREG, d = 1: store result in file register f.
PIC18FXX2 FIGURE 20-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 ADDWF MYREG, W, B f (FILE #) d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f = 12-bi
PIC18FXX2 TABLE 20-2: PIC18FXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f, d
PIC18FXX2 TABLE 20-2: PIC18FXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s CLRWDT DAW GOTO — — n NOP NOP POP PUSH RCALL RESET RETFIE — — — — n RETLW RETURN SLEEP 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero B
PIC18FXX2 TABLE 20-2: PIC18FXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSRx 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from liter
PIC18FXX2 20.1 Instruction Set ADDLW ADD literal to W Syntax: [ label ] ADDLW Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 Description: 1111 kkkk kkkk The contents of W are added to the 8-bit literal 'k' and the result is placed in W.
PIC18FXX2 ADDWFC ADD W and Carry bit to f ANDLW AND literal with W Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f [,d [,a] Operation: (W) + (f) + (C) → dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 1 Cycles: 1 0 ≤ k ≤ 255 Operation: (W) .AND. k → W Status Affected: N,Z Encoding: ffff ffff Add W, the Carry Flag and data memory location 'f'. If 'd' is 0, the result is placed in W.
PIC18FXX2 ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f [,d [,a] Operation: (W) .AND.
PIC18FXX2 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 0 → f Status Affected: None Encoding: 1001 Description: Branch if Negative Syntax: [ label ] BN Operands: -128 ≤ n ≤ 127 Operation: if negative bit is ’1’ (PC) + 2 + 2n → PC Status Affected: None Encoding: bbba ffff ffff 1110 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register 'f' Process Data Write register 'f' Example: BCF Before Instruction FLAG_REG = 0xC7 After I
PIC18FXX2 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC Syntax: [ label ] BNN Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if carry bit is ’0’ (PC) + 2 + 2n → PC Operation: if negative bit is ’0’ (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 n 0011 nnnn nnnn Encoding: 1110 n 0111 nnnn nnnn Description: If the Carry bit is ’0’, then the program will branch.
PIC18FXX2 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV Syntax: [ label ] BNZ Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if overflow bit is ’0’ (PC) + 2 + 2n → PC Operation: if zero bit is ’0’ (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 n 0101 nnnn nnnn Encoding: 1110 n 0001 nnnn nnnn Description: If the Overflow bit is ’0’, then the program will branch.
PIC18FXX2 BRA Unconditional Branch BSF Bit Set f Syntax: [ label ] BRA Syntax: [ label ] BSF Operands: -1024 ≤ n ≤ 1023 Operands: Operation: (PC) + 2 + 2n → PC Status Affected: None 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 1 → f Status Affected: None Encoding: Description: 1101 1 Cycles: 2 Q Cycle Activity: Q1 No operation 0nnn nnnn nnnn Add the 2’s complement number ’2n’ to the PC.
PIC18FXX2 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit 'b' in register ’f' is 0, then the next instruction is skipped.
PIC18FXX2 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if overflow bit is ’1’ (PC) + 2 + 2n → PC Status Affected: None Operation: (f) → f Status Affected: None Encoding: Description: bbba ffff 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register 'f' Process Data Write register 'f' Example: BTG PORTC, = 0111 0101 [0x75] After Instruction: PORT
PIC18FXX2 BZ Branch if Zero CALL Subroutine Call Syntax: [ label ] BZ Syntax: [ label ] CALL k [,s] Operands: -128 ≤ n ≤ 127 Operands: Operation: if Zero bit is ’1’ (PC) + 2 + 2n → PC 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: (PC) + 4 → TOS, k → PC<20:1>, if s = 1 (W) → WS, (STATUS) → STATUSS, (BSR) → BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ’1’, then the program will branch.
PIC18FXX2 CLRF Clear f Syntax: [ label ] CLRF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: 000h → f 1→Z Status Affected: Z Encoding: Description: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h → WDT, 000h → WDT postscaler, 1 → TO, 1 → PD Status Affected: TO, PD Encoding: 0000 0000 0000 0100 Clears the contents of the specified register. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value.
PIC18FXX2 COMF Complement f Syntax: [ label ] COMF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: ( f ) → dest Status Affected: N, Z Encoding: 0001 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Syntax: [ label ] CPFSEQ Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None Encoding: 0110 001a f [,a] ffff ffff Description: Compares the contents of data memory location 'f' to the contents of W by performing an u
PIC18FXX2 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: [ label ] CPFSGT Syntax: [ label ] CPFSLT Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) − (W), skip if (f) > (W) (unsigned comparison) Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 010a f [,a] ffff ffff Compares the contents of data memory location 'f' to the contents
PIC18FXX2 DAW Decimal Adjust W Register DECF Decrement f Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a] Operands: None Operands: Operation: If [W<3:0> >9] or [DC = 1] then (W<3:0>) + 6 → W<3:0>; else (W<3:0>) → W<3:0>; 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z If [W<7:4> >9] or [C = 1] then (W<7:4>) + 6 → W<7:4>; else (W<7:4>) → W<7:4>; Status Affected: Encoding: 0000 0000 0000 1 Cycles: 1 Q Cycle Activity: Q1 Q3 Q4 Proces
PIC18FXX2 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da f [,d [,a] ffff ffff Description: The contents of register 'f' are decreme
PIC18FXX2 GOTO Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 1048575 Operands: Operation: k → PC<20:1> Status Affected: None 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: 1110 1111 GOTO k 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch anywhere within entire 2 Mbyte memory range.
PIC18FXX2 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, skip if result = 0 Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 INCFSZ 11da f [,d [,a] ffff ffff Encoding: 0100 INFSNZ 10da f [,d [,a] ffff ffff Description: The contents of register 'f' are incre
PIC18FXX2 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .OR. (f) → dest Status Affected: N, Z IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR.
PIC18FXX2 LFSR Load FSR MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0≤f≤2 0 ≤ k ≤ 4095 Operands: Operation: k → FSRf 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: f → dest Status Affected: N, Z Encoding: LFSR f,k 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal 'k' is loaded into the file select register pointed to by 'f'.
PIC18FXX2 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operands: 0 ≤ k ≤ 255 Operation: k → BSR None MOVFF fs,fd Operation: (fs) → fd Status Affected: Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register 'fs' are moved to destination register 'fd'.
PIC18FXX2 MOVLW Move literal to W MOVWF Move W to f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k→W 0 ≤ f ≤ 255 a ∈ [0,1] Status Affected: None Operation: (W) → f Status Affected: None Encoding: 0000 Description: MOVLW k 1110 kkkk The eight-bit literal 'k' is loaded into W.
PIC18FXX2 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None MULLW k Operands: 0 ≤ k ≤ 255 Operation: (W) x k → PRODH:PRODL Status Affected: None Encoding: Description: 0000 1 Cycles: 1 Q Cycle Activity: Q1 Example: kkkk Q2 Q3 Q4 Read literal 'k' Process Data Write registers PRODH: PRODL MULLW 0xC4 W PRODH PRODL Encoding: = = = 0xE2 ? ? = =
PIC18FXX2 NEGF Negate f Syntax: [ label ] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] NEGF Operation: (f)+1→f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None 0000 1111 ffff Description: 1 Cycles: 1 Decode 0000 xxxx 0000 xxxx No operation.
PIC18FXX2 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC+2) → TOS Status Affected: None Status Affected: None Encoding: 0000 Description: 0000 0000 0110 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18FXX2 RCALL Relative Call RESET Reset Syntax: [ label ] RCALL Syntax: [ label ] Operands: Operation: -1024 ≤ n ≤ 1023 Operands: None (PC) + 2 → TOS, (PC) + 2 + 2n → PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: Description: 1101 nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack.
PIC18FXX2 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: [ label ] Syntax: [ label ] RETFIE [s] RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL, if s = 1 (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged.
PIC18FXX2 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] RETURN [s] RLCF f [,d [,a] Operands: s ∈ [0,1] Operands: Operation: (TOS) → PC, if s = 1 (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z None Encoding: Status Affected: Encoding: 0000 0000 0001 001s Description: Return from subroutine.
PIC18FXX2 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → dest<0> Operation: Status Affected: N, Z (f) → dest, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0100 Description: RLNCF 01da f [,d [,a] ffff ffff The contents of register 'f' are rotated one bit to the left.
PIC18FXX2 RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] Syntax: [ label ] SETF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) → dest, (f<0>) → dest<7> FFh → f Operation: Status Affected: None Status Affected: N, Z Encoding: 0100 Description: RRNCF 00da f [,d [,a] Encoding: ffff ffff The contents of register 'f' are rotated one bit to the right. If 'd' is 0, the result is placed in W.
PIC18FXX2 SLEEP Enter SLEEP mode SUBFWB Subtract f from W with borrow Syntax: [ label ] SLEEP Syntax: [ label ] SUBFWB Operands: None Operands: Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z TO, PD Encoding: Status Affected: Encoding: 0000 0000 0000 0011 Description: The power-down status bit (PD) is cleared. The time-out status bit (TO) is set.
PIC18FXX2 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k – (W) → W Status Affected: N, OV, C, DC, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal 'k'. The result is placed in W.
PIC18FXX2 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: [ label ] SUBWFB Syntax: [ label ] SWAPF f [,d [,a] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: None Encoding: Description: 0101 ffff ffff Subtract W and the carry flag (borrow) from register 'f' (2’s complement method).
PIC18FXX2 TBLRD Table Read TBLRD Table Read (cont’d) Syntax: [ label ] Example1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT; TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT; (TBLPTR) +1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT; (TBLPTR) -1 → TBLPTR; if TBLRD +*, (TBLPTR) +1 → TBLPTR; (Prog Mem (TBLPTR)) → TABLAT; TBLRD ( *; *+; *-; +*) Before Instruction Status Affected:None Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +* Descrip
PIC18FXX2 TBLWT Table Write TBLWT Table Write (Continued) Syntax: [ label ] Example1: TBLWT TBLWT ( *; *+; *-; +*) Before Instruction Operands: None Operation: if TBLWT*, (TABLAT) → Holding Register; TBLPTR - No Change; if TBLWT*+, (TABLAT) → Holding Register; (TBLPTR) +1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register; (TBLPTR) -1 → TBLPTR; if TBLWT+*, (TBLPTR) +1 → TBLPTR; (TABLAT) → Holding Register; Status Affected: None Encoding: Description: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3
PIC18FXX2 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: [ label ] TSTFSZ f [,a] Syntax: [ label ] XORLW k Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: Operation: skip if f = 0 (W) .XOR. k → W Status Affected: N, Z Status Affected: None Encoding: Description: Encoding: 0110 011a ffff ffff If 'f' = 0, the next instruction, fetched during the current instruction execution, is discarded and a NOP is executed, making this a twocycle instruction.
PIC18FXX2 XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da f [,d [,a] ffff ffff Description: Exclusive OR the contents of W with register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in the register 'f' (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value.
PIC18FXX2 21.
PIC18FXX2 21.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker.
PIC18FXX2 21.8 MPLAB ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices.
PIC18FXX2 21.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs.
Software Tools Programmers Debugger Emulators PIC12CXXX PIC14000 PIC16C5X PIC16C6X PIC16CXXX PIC16F62X PIC16C7X ! ! ! ! ! ! © 2006 Microchip Technology Inc. ! ! ! † † ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! MCP2510 * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
PIC18FXX2 NOTES: DS39564C-page 258 © 2006 Microchip Technology Inc.
PIC18FXX2 22.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.
PIC18FXX2 FIGURE 22-1: PIC18FXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18FXXX Voltage 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 22-2: PIC18LFXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LFXXX 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application. DS39564C-page 260 © 2006 Microchip Technology Inc.
PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) PIC18LFXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol No. VDD D001 Characteristic Min Typ Max Units PIC18LFXX2 2.0 — 5.
PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) PIC18LFXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol No. IDD Characteristic Min Typ Max Units Conditions — — — .5 .5 1.
PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) PIC18LFXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol No.
PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) PIC18LFXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18FXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol No.
PIC18FXX2 22.2 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions with TTL buffer Vss 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V ≤ VDD ≤ 5.5V with Schmitt Trigger buffer RC3 and RC4 Vss Vss 0.2 VDD 0.
PIC18FXX2 22.2 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param Symbol No. VOL D080 Characteristic D080A OSC2/CLKO (RC mode) D083A VOH D090 D090A OSC2/CLKO (RC mode) D092A D150 VOD Units Conditions — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C — 0.6 V IOL = 7.0 mA, VDD = 4.
PIC18FXX2 FIGURE 22-3: LOW VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) 37 LVDIF TABLE 22-1: LOW VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Symbol No. D420 VLVD Characteristic Min Typ Max Units Conditions LVD Voltage on VDD LVV = 0001 transition high to LVV = 0010 low LVV = 0011 1.98 2.06 2.
PIC18FXX2 TABLE 22-2: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC Characteristics Param No. Sym Characteristic Min Typ† Max Units Conditions 9.00 — 13.
PIC18FXX2 22.3 22.3.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18FXX2 22.3.2 TIMING CONDITIONS The temperature and voltages specified in Table 22-3 apply to all timing specifications unless otherwise noted. Figure 22-4 specifies the load conditions for the timing specifications.
PIC18FXX2 22.3.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 22-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 22-4: Param. No.
PIC18FXX2 TABLE 22-5: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V) Sym Characteristic Min Typ† Max 4 16 — — 10 40 Units — — FOSC Oscillator Frequency Range FSYS On-chip VCO System Frequency — trc PLL Start-up Time (Lock Time) — — 2 ms — ΔCLK CLKO Stability (Jitter) -2 — +2 % Conditions MHz HS mode only MHz HS mode only † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
PIC18FXX2 TABLE 22-6: CLKO AND I/O TIMING REQUIREMENTS Param. Symbol No. Characteristic Min Typ Max Units Conditions 10 TosH2ckL OSC1↑ to CLKO↓ — 75 200 ns (Note 1) 11 TosH2ckH OSC1↑ to CLKO↑ — 75 200 ns (Note 1) 12 TckR CLKO rise time — 35 100 ns (Note 1) 13 TckF CLKO fall time — 35 100 ns (Note 1) 14 TckL2ioV CLKO↓ to Port out valid — — 0.
PIC18FXX2 FIGURE 22-8: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V Typical VIRVST Enable Internal Reference Voltage Internal Reference Voltage stable TABLE 22-7: 36 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No.
PIC18FXX2 FIGURE 22-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 22-4 for load conditions. TABLE 22-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol No. 40 Tt0H Characteristic T0CKI High Pulse Width Min Max Units 0.5TCY + 20 — ns 10 — ns 0.5TCY + 20 — ns 10 — ns TCY + 10 — ns Greater of: 20 nS or TCY + 40 N — ns 0.
PIC18FXX2 FIGURE 22-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: TABLE 22-9: Refer to Figure 22-4 for load conditions. CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param. Symbol No. 50 51 TccL TccH Characteristic Min Max Units CCPx input low No Prescaler time With PIC18FXXX Prescaler PIC18LFXXX 0.5 TCY + 20 — ns 10 — ns 20 — ns CCPx input high time 0.
PIC18FXX2 FIGURE 22-11: PARALLEL SLAVE PORT TIMING (PIC18F4X2) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 22-4 for load conditions. TABLE 22-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X2) Param. No. 62 63 64 Symbol TdtV2wrH TwrH2dtI TrdL2dtV Characteristic Min Max Units Conditions Data in valid before WR↑ or CS↑ (setup time) 20 25 — — ns ns Extended Temp.
PIC18FXX2 FIGURE 22-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 bit6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In bit6 - - - -1 LSb In 74 73 Note: Refer to Figure 22-4 for load conditions. TABLE 22-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param. No.
PIC18FXX2 FIGURE 22-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO bit6 - - - - - -1 LSb bit6 - - - -1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 22-4 for load conditions. TABLE 22-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. 71 Symbol TscH SCK input high time (Slave mode) TscL SCK input low time (Slave mode) 71A 72 Characteristic 72A Min Max Units Conditions 1.
PIC18FXX2 FIGURE 22-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit6 - - - - - -1 LSb 77 75, 76 SDI MSb In bit6 - - - -1 LSb In 74 73 Note: Refer to Figure 22-4 for load conditions. TABLE 22-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)) Param. No.
PIC18FXX2 FIGURE 22-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS 70 SCK (CKP = 0) 83 71 72 SCK (CKP = 1) 80 MSb SDO bit6 - - - - - -1 LSb 75, 76 SDI MSb In 77 bit6 - - - -1 LSb In 74 Note: Refer to Figure 22-4 for load conditions. TABLE 22-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param. No. Symbol Characteristic 70 TssL2scH, SS↓ to SCK↓ or SCK↑ input TssL2scL 71 TscH 71A 72 SCK input high time (Slave mode) Min Max Units Conditions TCY — ns ns Continuous 1.
PIC18FXX2 FIGURE 22-16: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 22-4 for load conditions. TABLE 22-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18FXX2 TABLE 22-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH Characteristic Clock high time Min Max Units Conditions 100 kHz mode 4.0 — μs PIC18FXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs PIC18FXXX must operate at a minimum of 10 MHz 1.5 TCY — 100 kHz mode 4.7 — μs PIC18FXXX must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs PIC18FXXX must operate at a minimum of 10 MHz SSP Module 101 TLOW Clock low time 1.
PIC18FXX2 FIGURE 22-18: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure 22-4 for load conditions. TABLE 22-17: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18FXX2 TABLE 22-18: MASTER SSP I2C BUS DATA REQUIREMENTS Param. Symbol No. 100 THIGH Characteristic Clock high time Min Max Units 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms 1 MHz mode 101 TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.
PIC18FXX2 FIGURE 22-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 Note: 122 Refer to Figure 22-4 for load conditions. TABLE 22-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. No.
PIC18FXX2 TABLE 22-21: A/D CONVERTER CHARACTERISTICS: PIC18FXX2 (INDUSTRIAL, EXTENDED) PIC18LFXX2 (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units Conditions A01 NR Resolution — — 10 A03 EIL Integral linearity error — — <±1 A04 EDL Differential linearity error — — <±1 LSb VREF = VDD = 5.0V A05 EG Gain error — — <±1 LSb VREF = VDD = 5.0V A06 EOFF Offset error — — <±1.5 LSb VREF = VDD = 5.
PIC18FXX2 TABLE 22-22: A/D CONVERSION REQUIREMENTS Param Symbol No. 130 TAD Characteristic A/D clock period Min Max Units PIC18FXXX 1.6 20(4) μs TOSC based PIC18FXXX 2.0 6.0 μs A/D RC mode 131 TCNV Conversion time (not including acquisition time) (Note 1) 11 12 TAD 132 TACQ Acquisition time (Note 2) 5 10 — — μs μs 135 TSWC Switching Time from convert → sample — (Note 3) Conditions VREF = VDD = 5.0V VREF = VDD = 2.
PIC18FXX2 23.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC18FXX2 FIGURE 23-3: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE) 20 18 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 16 5.5V 14 5.0V 4.5V IDD (mA) 12 10 4.2V 8 6 4 2 0 4 5 6 7 8 9 10 FOSC (MHz) FIGURE 23-4: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) 20 18 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 16 5.5V 5.0V 14 4.5V IDD (mA) 12 4.
PIC18FXX2 FIGURE 23-5: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 2,000 1,800 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 5.5V 1,600 5.0V 1,400 4.5V IIDD μA) DD ((uA) 1,200 4.0V 1,000 3.5V 3.0V 800 2.5V 600 2.0V 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 23-6: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 2,000 5.
PIC18FXX2 FIGURE 23-7: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 100 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 90 80 5.5V 70 5.0V IDD (uA) 60 4.5V 50 4.0V 40 3.5V 3.0V 30 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 90 100 FOSC (kHz) FIGURE 23-8: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 140 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 120 5.5V 5.0V 100 4.
PIC18FXX2 FIGURE 23-9: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 16 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 14 5.5V 5.0V 12 4.5V 4.2V IDD (mA) 10 4.0V 8 6 3.5V 4 3.0V 2 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 23-10: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) 16 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 14 5.5V 5.0V 12 4.5V 4.
PIC18FXX2 FIGURE 23-11: TYPICAL AND MAXIMUM IDD vs. VDD (TIMER1 AS MAIN OSCILLATOR, 32.768 kHz, C1 AND C2 = 47 pF) 180 160 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-10°C to 70°C) Minimum: mean – 3σ (-10°C to 70°C) 140 IDD (μA) PD (uA) 120 100 Max Max(+70°C) (70C) 80 60 Typ Typ(+25°C) (25C) 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-12: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, +25°C) 4,500 Operation above 4 MHz is not recommended.
PIC18FXX2 FIGURE 23-13: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, +25°C) 2,000 1,800 1,600 3.3kΩ 1,400 Freq (kHz) 1,200 5.1kΩ 1,000 800 10k Ω 600 400 200 100kΩ 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 23-14: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, +25°C) 800 700 3.3kΩ 600 Freq (MHz) 500 5.1kΩ 400 300 10kΩ 200 100 100kΩ 0 2.0 2.5 3.0 3.5 4.0 4.5 VDD (V) © 2006 Microchip Technology Inc.
PIC18FXX2 FIGURE 23-15: IPD vs. VDD, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Max (-40°C to +125°C) 10 IPD (uA) Max (+85°C) 1 Typ (+25°C) 0.1 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-16: ΔIBOR vs. VDD OVER TEMPERATURE (BOR ENABLED, VBOR = 2.00 - 2.
PIC18FXX2 FIGURE 23-17: TYPICAL AND MAXIMUM ΔITMR1 vs. VDD OVER TEMPERATURE (-10°C TO +70°C, TIMER1 WITH OSCILLATOR, XTAL = 32 kHz, C1 AND C2 = 47 pF) 14 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-10°C to 70°C) Minimum: mean – 3σ (-10°C to 70°C) 12 Max(+70°C) (70C) Max 10 IPD (uA) (μA) 8 Typ Typ(+25°C) (25C) 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-18: TYPICAL AND MAXIMUM ΔIWDT vs.
PIC18FXX2 FIGURE 23-19: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO +125°C) 50 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 45 40 Max Max (+125°C) (125C) 35 WDT Period (ms) Max MAX (+85°C) (85C) 30 25 Typ (+25°C) (25C) 20 15 Min Min (-40°C) (-40C) 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-20: ΔILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 4.5 - 4.
PIC18FXX2 FIGURE 23-21: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C) 5.5 5.0 4.5 Max Max 4.0 Typ Typ(+25°C) (25C) VOH (V) 3.5 3.0 Min Min 2.5 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 23-22: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C) 3.0 2.5 2.0 VOH (V) Max Max 1.5 Typ Typ(+25°C) (25C) 1.0 Min Min 0.5 0.0 0 5 10 15 20 25 IOH (-mA) © 2006 Microchip Technology Inc.
PIC18FXX2 FIGURE 23-23: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C) 1.8 1.6 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 1.4 VOL (V) 1.2 1.0 Max Max 0.8 0.6 0.4 Typ (+25°C) Typ (25C) 0.2 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 23-24: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C) 2.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 2.
PIC18FXX2 FIGURE 23-25: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C) 4.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 3.5 VIH Max 3.0 2.5 VIN (V) VIH Min 2.0 VIL Max 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-26: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40°C TO +125°C) 1.
PIC18FXX2 MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40°C TO +125°C) FIGURE 23-27: 3.5 VIH Max Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 3.0 2.5 2.0 VIN (V) VILMax VIH Min 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) A/D NON-LINEARITY vs. VREFH (VDD = VREFH, -40°C TO +125°C) FIGURE 23-28: 4 3.5 Differential or Integral Nonlinearity (LSB) -40°C -40C 3 +25°C 25C 2.5 +85°C 85C 2 1.5 1 0.
PIC18FXX2 FIGURE 23-29: A/D NON-LINEARITY vs. VREFH (VDD = 5V, -40°C TO +125°C) 3 Differential or Integral Nonlinearilty (LSB) 2.5 2 1.5 Max +125°C) Max (-40°C (-40C toto125C) 1 Typ Typ (+25°C) (25C) 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VREFH (V) © 2006 Microchip Technology Inc.
PIC18FXX2 NOTES: DS39564C-page 304 © 2006 Microchip Technology Inc.
PIC18FXX2 24.0 PACKAGING INFORMATION 24.1 Package Marking Information 28-Lead SPDIP Example PIC18F242-I/SP e3 0610017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...
PIC18FXX2 Package Marking Information (Cont’d) 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS39564C-page 306 Example PIC18F452 -E/PT e3 0610017 Example PIC18F442 -I/L e3 0610017 © 2006 Microchip Technology Inc.
PIC18FXX2 24.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 α E A2 A L c β B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN 28 NOM MAX 28 .100 2.54 Top to Seating Plane A .140 .
PIC18FXX2 28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 1 n h α 45° c A2 A φ β L Units Dimension Limits n p A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MAX MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.
PIC18FXX2 40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D α 2 1 n E A2 A L c β B1 A1 eB p B Units Dimension Limits n p INCHES* NOM 40 .100 .175 .150 MAX MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.
PIC18FXX2 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 1 B n CH x 45° α A c φ β A1 L Units Dimension Limits n p Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) n1 A A2 A1 L F φ MIN .039 .037 .002 .018 INCHES NOM 44 .
PIC18FXX2 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n 1 2 CH2 x 45 ° CH1 x 45 ° α A3 A2 35° A B1 B c β E2 Units Dimension Limits n p A1 p D2 INCHES* MIN NOM 44 .050 11 .165 .173 .145 .153 .028 .020 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .013 .
PIC18FXX2 NOTES: DS39564C-page 312 © 2006 Microchip Technology Inc.
PIC18FXX2 APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (June 2001) DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Original data sheet for the PIC18FXX2 family. Revision B (August 2002) This revision includes the DC and AC Characteristics Graphs and Tables. The Electrical Specifications in Section 22.0 have been updated and there have been minor corrections to the data sheet text. Revision C (October 2006) Packaging diagrams updated.
PIC18FXX2 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable DS39564C-page 314 APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a Baseline device (i.e.
PIC18FXX2 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18F442”. The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations.
PIC18FXX2 NOTES: DS39564C-page 316 © 2006 Microchip Technology Inc.
PIC18FXX2 INDEX A A/D ................................................................................... 181 A/D Converter Flag (ADIF Bit) ................................. 183 A/D Converter Interrupt, Configuring ....................... 184 Acquisition Requirements ........................................ 184 ADCON0 Register .................................................... 181 ADCON1 Register .................................................... 181 ADRESH Register .....................................
PIC18FXX2 C D CALL ................................................................................ 226 Capture (CCP Module) ..................................................... 119 Associated Registers ............................................... 121 CCP Pin Configuration ............................................. 119 CCPR1H:CCPR1L Registers ................................... 119 Software Interrupt ..................................................... 119 Timer1/Timer3 Mode Selection ............
PIC18FXX2 I I/O Ports ............................................................................. 87 I2C (MSSP Module) ACK Pulse ................................................................ 139 Read/Write Bit Information (R/W Bit) ....................... 139 I2C (SSP Module) ACK Pulse ................................................................ 138 I2C Master Mode Reception ............................................. 155 I2C Mode Clock Stretching .................................................
PIC18FXX2 TBLRD ..................................................................... 249 TBLWT ..................................................................... 250 TSTFSZ .................................................................... 251 XORLW .................................................................... 251 XORWF .................................................................... 252 Summary Table ........................................................
PIC18FXX2 P Packaging ........................................................................ 305 Details ...................................................................... 307 Marking Information ................................................. 305 Parallel Slave Port PORTD .................................................................... 100 Parallel Slave Port (PSP) ........................................... 95, 100 Associated Registers ...............................................
PIC18FXX2 PORTE Analog Port Pins ................................................ 99, 100 Associated Registers ................................................. 99 LATE Register ............................................................ 97 PORTE Register ........................................................ 97 PSP Mode Select (PSPMODE Bit) .................... 95, 100 RE0/RD/AN5 Pin ................................................ 99, 100 RE1/WR/AN6 Pin ...............................................
PIC18FXX2 RETFIE ............................................................................ 242 RETLW ............................................................................. 242 RETURN .......................................................................... 243 Revision History ............................................................... 313 RLCF ................................................................................ 243 RLNCF ...........................................................
PIC18FXX2 Example SPI Master Mode (CKE = 0) ..................... 278 Example SPI Master Mode (CKE = 1) ..................... 279 Example SPI Slave Mode (CKE = 0) ....................... 280 Example SPI Slave Mode (CKE = 1) ....................... 281 External Clock (All Modes except PLL) .................... 271 First START Bit Timing ............................................ 153 I2C Bus Data ............................................................ 282 I2C Bus START/STOP Bits .......................
PIC18FXX2 W X Wake-up from SLEEP .............................................. 195, 205 Using Interrupts ........................................................ 205 Watchdog Timer (WDT) ........................................... 195, 203 Associated Registers ............................................... 204 Control Register ....................................................... 203 Postscaler ........................................................ 203, 204 Programming Considerations ...............
PIC18FXX2 NOTES: DS39564C-page 326 © 2006 Microchip Technology Inc.
PIC18FXX2 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC18FXX2 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC18FXX2 PIC18FXX2 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. − PART NO. Device Device X Temperature Range /XX XXX Package Pattern PIC18FXX2(1), PIC18FXX2T(2); VDD range 4.2V to 5.5V PIC18LFXX2(1), PIC18LFXX2T(2); VDD range 2.5V to 5.
WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.
