Datasheet

PIC18F46J11 FAMILY
DS39932D-page 94  2011 Microchip Technology Inc.
PMDOUT2H
(5)
Parallel Port Out Data High Byte (Buffer 3) 0000 0000 73
PMDOUT2L
(5)
Parallel Port Out Data Low Byte (Buffer 2) 0000 0000 73
PMDIN2H
(5)
Parallel Port In Data High Byte (Buffer 3) 0000 0000 73
PMDIN2L
(5)
Parallel Port In Data Low Byte (Buffer 2) 0000 0000 73
PMEH
(5)
PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 0000 0000 73, 176
PMEL
(5)
PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000 0000 73, 176
PMSTATH
(5)
IBF IBOV — — IB3F IB2F IB1F IB0F 00-- 0000 73, 177
PMSTATL
(5)
OBE OBUF — — OB3E OB2E OB1E OB0E 10-- 1111 73, 177
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 73, 370
TCLKCON
— — — T1RUN — — T3CCP2 T3CCP1 ---0 --00 203
DSGPR1 Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep) uuuu uuuu 59
DSGPR0 Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep) uuuu uuuu 59
DSCONH DSEN
— — — — (Reserved) DSULPEN RTCWDIS 0--- -000 58
DSCONL
— — — — — ULPWDIS DSBOR RELEASE ---- -000 58
DSWAKEH
— — — — — — —DSINT0---- ---0 60
DSWAKEL DSFLT
— DSULP DSWDT DSRTC DSMCLR — DSPOR 0-00 00-1 60
ANCON1 VBGEN
r — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 00-0 0000 73, 353
ANCON0 PCFG7
(5)
PCFG6
(5)
PCFG5
(5)
PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 73, 353
ODCON1
— — — — — — ECCP20D ECCP10D ---- --00 73, 133
ODCON2
— — — — — —U2ODU1OD---- --00 73, 133
ODCON3
— — — — — — SPI2OD SPI1OD ---- --00 73, 134
RTCCFG RTCEN
— RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0-00 0000 73, 229
RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000 0000 73, 230
REFOCON ROON
— ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 0-00 0000 73, 45
PADCFG1
— — — — — RTSECSEL1 RTSECSEL0 PMPTTL ---- -000 73, 134
PPSCON
— — — — — — — IOLOCK ---- ---0 155
RPINR24
— — — Input Function FLT0 to Input Pin Mapping Bits ---1 1111 74, 160
RPINR23
— — — Input Function SS2 to Input Pin Mapping Bits ---1 1111 74, 160
RPINR22
— — — Input Function SCK2 to Input Pin Mapping Bits ---1 1111 74, 160
RPINR21
— — — Input Function SDI2 to Input Pin Mapping Bits ---1 1111 74, 159
RPINR17
— — — Input Function CK2 to Input Pin Mapping Bits ---1 1111 74, 159
RPINR16
— — — Input Function RX2DT2 to Input Pin Mapping Bits ---1 1111 159
RPINR13
— — — Input Function T3G to Input Pin Mapping Bits ---1 1111 75, 158
RPINR12
— — — Input Function T1G to Input Pin Mapping Bits ---1 1111 75, 158
RPINR8
— — — Input Function IC2 to Input Pin Mapping Bits ---1 1111 75, 158
RPINR7
— — — Input Function IC1 to Input Pin Mapping Bits ---1 1111 75, 157
RPINR6
— — — Input Function T3CKI to Input Pin Mapping Bits ---1 1111 75, 157
RPINR4
— — — Input Function T0CKI to Input Pin Mapping Bits ---1 1111 75, 157
RPINR3
— — — Input Function INT3 to Input Pin Mapping Bits ---1 1111 75, 156
RPINR2
— — — Input Function INT2 to Input Pin Mapping Bits ---1 1111 75
RPINR1
— — — Input Function INT1 to Input Pin Mapping Bits ---1 1111 75, 156
RPOR24
(5)
— — — Remappable Pin RP24 Output Signal Select Bits ---0 0000 74, 169
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes.
2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
4: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 19.5.3.2 “Address
Masking Modes” for details.
5: These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for
44-pin devices.
6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.