Datasheet

 2011 Microchip Technology Inc. DS39932D-page 93
PIC18F46J11 FAMILY
DMACON2 DLYCYC3 DLYCYC2 DLYCYC1 DLYCYC0 INTLVL3 INTLVL2 INTLVL1 INTLVL0 0000 0000 72, 285
HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000 0000 72
PORTE RDPU REPU
— — — RE2 RE1 RE0 00-- -xxx 72
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 72
PORTC RC7 RC6 RC5 RC4 RC4 RC2 RC1 RC0 xxxx xxxx 72
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 72
PORTA RA7 RA6 RA5
— RA3 RA2 RA1 RA0 xxx- xxxx 72
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 72
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN 0100 0-00 72, 330
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 0000 0000 72
BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN 0100 0-00 72, 330
TMR3H Timer3 Register High Byte xxxx xxxx 73
TMR3L Timer3 Register Low Byte xxxx xxxx 73
T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0
— T3SYNC RD16 TMR3ON 0000 -000 73, 215
TMR4 Timer4 Register 0000 0000 73
PR4 Timer4 Period Register 1111 1111 73
T4CON
— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 73, 225
SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 73
SSP2ADD/
SSP2MSK
(4)
MSSP2 Address Register (I
2
C™ Slave mode), MSSP2 Baud Rate Reload Register (I
2
C Master mode) 0000 0000 73, 295
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 73, 295
SSP2STAT SMP CKE D/A
PSR/WUA BF 0000 0000 73, 273
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 73, 293
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 73, 294
GCEN ACKSTAT ADMSK5
(4)
ADMSK4
(4)
ADMSK3
(4)
ADMSK2
(4)
ADMSK1
(4)
SEN
CMSTAT
— — — — — — COUT2 COUT1 ---- --11 73, 363
PMADDRH/
— CS1 Parallel Master Port Address High Byte -000 0000 73, 179
PMDOUT1H
(5)
Parallel Port Out Data High Byte (Buffer 1) 0000 0000 73, 179
PMADDRL/ Parallel Master Port Address Low Byte 0000 0000 73, 179
PMDOUT1L
(5)
Parallel Port Out Data Low Byte (Buffer 0) 0000 0000 73, 179
PMDIN1H
(5)
Parallel Port In Data High Byte (Buffer 1) 0000 0000 73
PMDIN1L
(5)
Parallel Port In Data Low Byte (Buffer 0) 0000 0000 73
TXADDRL SPI DMA Transit Data Pointer Low Byte 0000 0000 73
TXADDRH
— — — — SPI DMA Transit Data Pointer High Byte ---- 0000 73
RXADDRL SPI DMA Receive Data Pointer Low Byte 0000 0000 73
RXADDRH
— — — — SPI DMA Receive Data Pointer High Byte ---- 0000 73
DMABCL SPI DMA Byte Count Low Byte 0000 0000 73
DMABCH
— — — — — — SPI DMA Receive Data
Pointer High Byte
---- --00 73
PMCONH
(5)
PMPEN — — ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 0--0 0000 73, 172
PMCONL
(5)
CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 000- 0000 73, 173
PMMODEH
(5)
BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 0000 0000 73, 174
PMMODEL
(5)
WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000 0000 73, 175
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J11 FAMILY)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Note 1: Bit 21 of the PC is only available in Serial Programming (SP) modes.
2: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
3: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
4: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 19.5.3.2 “Address
Masking Modes” for details.
5: These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are shown for
44-pin devices.
6: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.