Datasheet

PIC18F46J11 FAMILY
DS39932D-page 530  2011 Microchip Technology Inc.
Asynchronous Transmission (Back-to-Back) ........... 338
Automatic Baud Rate Calculation ............................336
Auto-Wake-up Bit (WUE) During Normal Operation 341
Auto-Wake-up Bit (WUE) During Sleep ................... 341
Baud Rate Generator with Clock Arbitration ............ 314
BRG Overflow Sequence ......................................... 336
BRG Reset Due to SDAx Arbitration During Start
Condition .......................................................... 322
Bus Collision During a Repeated Start Condition
(Case 1) ........................................................... 323
Bus Collision During a Repeated Start Condition
(Case 2) ........................................................... 323
Bus Collision During a Start Condition (SCLx = 0) ... 322
Bus Collision During a Stop Condition (Case 1) ...... 324
Bus Collision During a Stop Condition (Case 2) ...... 324
Bus Collision During Start Condition (SDAx Only) ... 321
Bus Collision for Transmit and Acknowledge ........... 320
CLKO and I/O .......................................................... 488
Clock Synchronization .............................................307
Clock/Instruction Cycle .............................................. 82
Enhanced Capture/Compare/PWM ......................... 492
EUSARTx Synchronous Receive (Master/Slave) .... 504
EUSARTx Synchronous Transmission
(Master/Slave) .................................................. 504
Example SPI Master Mode (CKE = 0) ..................... 496
Example SPI Master Mode (CKE = 1) ..................... 497
Example SPI Slave Mode (CKE = 0) ....................... 498
Example SPI Slave Mode (CKE = 1) ....................... 499
External Clock .......................................................... 486
Fail-Safe Clock Monitor ............................................ 410
First Start Bit ............................................................ 314
Full-Bridge PWM Output .......................................... 260
Half-Bridge PWM Output ................................. 258, 265
High/Low-Voltage Detect Characteristics ................ 484
High-Voltage Detect (VDIRMAG = 1) ....................... 377
I
2
2C Bus Data .......................................................... 500
I
2
C Acknowledge Sequence .................................... 319
I
2
C Bus Start/Stop Bits ............................................. 500
I
2
C Master Mode (7 or 10-Bit Transmission) ........... 317
I
2
C Master Mode (7-Bit Reception) .......................... 318
I
2
C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001) ............................................. 303
I
2
C Slave Mode (10-Bit Reception, SEN = 0) .......... 304
I
2
C Slave Mode (10-Bit Reception, SEN = 1) .......... 309
I
2
C Slave Mode (10-Bit Transmission) ..................... 305
I
2
C Slave Mode (7-Bit Reception, SEN = 0,
ADMSK = 01011) ............................................. 301
I
2
C Slave Mode (7-Bit Reception, SEN = 0) ............ 300
I
2
C Slave Mode (7-Bit Reception, SEN = 1) ............ 308
I
2
C Slave Mode (7-Bit Transmission) ....................... 302
I
2
C Slave Mode General Call Address Sequence
(7 or 10-Bit Addressing Mode) ......................... 310
I
2
C Stop Condition Receive or Transmit Mode ........ 319
Low-Voltage Detect (VDIRMAG = 0) ....................... 376
MSSPx I
2
C Bus Data ...............................................502
MSSPx I
2
C Bus Start/Stop Bits ................................ 502
Parallel Master Port Read ........................................493
Parallel Master Port Write ........................................494
Parallel Slave Port Read .................................. 181, 183
Parallel Slave Port Write .................................. 181, 184
PWM Auto-Shutdown with Auto-Restart Enabled .... 264
PWM Auto-Shutdown with Firmware Restart ........... 264
PWM Direction Change ........................................... 261
PWM Direction Change at Near 100% Duty Cycle .. 262
PWM Output ............................................................ 252
PWM Output (Active-High) ...................................... 256
PWM Output (Active-Low) ....................................... 257
Read and Write, 8-Bit Data, Demultiplexed
Address ........................................................... 188
Read, 16-Bit Data, Demultiplexed Address ............. 191
Read, 16-Bit Multiplexed Data, Fully Multiplexed
16-Bit Address ................................................. 192
Read, 16-Bit Multiplexed Data, Partially Multiplexed
Address .......................................................... 191
Read, 8-Bit Data, Fully Multiplexed 16-Bit Address . 190
Read, 8-Bit Data, Partially Multiplexed Address ...... 188
Read, 8-Bit Data, Partially Multiplexed Address,
Enable Strobe .................................................. 189
Read, 8-Bit Data, Wait States Enabled, Partially
Multiplexed Address ........................................ 188
Repeated Start Condition ........................................ 315
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ..... 489
Send Break Character Sequence ............................ 342
Slave Synchronization ............................................. 278
Slow Rise Time (MCLR
Tied to VDD, VDD Rise >
T
PWRT) ............................................................... 67
SPI Mode (Master Mode) ......................................... 277
SPI Mode (Slave Mode, CKE = 0) ........................... 279
SPI Mode (Slave Mode, CKE = 1) ........................... 279
Steering Event at Beginning of Instruction
(STRSYNC = 1) ............................................... 268
Steering Event at End of Instruction
(STRSYNC = 0) ............................................... 268
Synchronous Reception (Master Mode, SREN) ...... 345
Synchronous Transmission ..................................... 343
Synchronous Transmission (Through TXEN) .......... 344
Time-out Sequence on Power-up (MCLR
Not
Tied to V
DD), Case 1 ......................................... 67
Time-out Sequence on Power-up (MCLR
Not
Tied to V
DD), Case 2 ......................................... 67
Time-out Sequence on Power-up (MCLR
Tied to
V
DD, VDD Rise < TPWRT) ................................... 66
Timer Pulse Generation ........................................... 244
Timer0 and Timer1 External Clock .......................... 491
Timer1 Gate Count Enable Mode ............................ 209
Timer1 Gate Single Pulse Mode .............................. 211
Timer1 Gate Single Pulse/Toggle Combined Mode 212
Timer1 Gate Toggle Mode ....................................... 210
Timer3 Gate Count Enable Mode) ........................... 219
Timer3 Gate Single Pulse Mode .............................. 221
Timer3 Gate Single Pulse/Toggle Combined Mode 222
Timer3 Gate Toggle Mode ....................................... 220
Transition for Entry to Idle Mode ................................ 53
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Two-Speed Start-up (INTRC to
HSPLL) ............................................................ 409
Transition for Wake From Idle to Run Mode .............. 53
Transition for Wake From Sleep (HSPLL) ................. 51
Transition From RC_RUN Mode to PRI_RUN Mode . 50
Transition From SEC_RUN Mode to PRI_RUN
Mode (HSPLL) ................................................... 49
Transition to RC_RUN Mode ..................................... 50
Write, 16-Bit Data, Demultiplexed Address ............. 191
Write, 16-Bit Multiplexed Data, Fully Multiplexed
16-Bit Address ................................................. 192
Write, 16-Bit Multiplexed Data, Partially Multiplexed
Address ........................................................... 192
Write, 8-Bit Data, Fully Multiplexed 16-Bit Address . 190