Datasheet

PIC18F46J11 FAMILY
DS39932D-page 406  2011 Microchip Technology Inc.
TABLE 26-3: SUMMARY OF WATCHDOG TIMER REGISTERS
REGISTER 26-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ACCESS FC0h)
R/W-1 R-x R-x U-0 R-0 R/W-0 R/W-0 R/W-0
REGSLP
(2)
LVDSTAT
(2)
ULPLVL —DS
(2)
ULPEN ULPSINK SWDTEN
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 REGSLP: Voltage Regulator Low-Power Operation Enable bit
(2)
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator is active even in Sleep mode
bit 6 LVDSTAT: Low-Voltage Detect Status bit
(2)
1 = VDDCORE > 2.45V nominal
0 = V
DDCORE < 2.45V nominal
bit 5 ULPLVL: Ultra Low-Power Wake-up Output bit (not valid unless ULPEN = 1)
1 = Voltage on RA0 > ~0.5V
0 = Voltage on RA0 < ~0.5V
bit 4 Unimplemented: Read as ‘0’
bit 3 DS: Deep Sleep Wake-up Status bit (used in conjunction with RCON, POR and BOR bits to determine
Reset source)
(2)
1 = If the last exit from POR was caused by a normal wake-up from Deep Sleep
0 = If the last exit from POR was a result of hard cycling V
DD, or if the Deep Sleep BOR was enabled
and detected, a (V
DD < VDSBOR) and (VDD < VPOR) condition
bit 2 ULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = Ultra Low-Power Wake-up module is enabled; ULPLVL bit indicates comparator output
0 = Ultra Low-Power Wake-up module is disabled
bit 1 ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit
1 = Ultra Low-Power Wake-up current sink is enabled (if ULPEN = 1)
0 = Ultra Low-Power Wake-up current sink is disabled
bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit
(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
2: Not available on devices where the on-chip voltage regulator is disabled (“LF” devices).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset Values
on Page:
RCON
IPEN — CM RI TO PD POR BOR 70
WDTCON REGSLP LVDSTAT ULPLVL
— DS ULPEN ULPSINK SWDTEN 70
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.