Datasheet

PIC18F46J11 FAMILY
DS39932D-page 38 2011 Microchip Technology Inc.
3.2.1 OSCILLATOR MODES
Figure 3-1 helps in understanding the oscillator
structure of the PIC18F46J11 family of devices.
FIGURE 3-1: PIC18F46J11 FAMILY CLOCK DIAGRAM
PIC18F46J11 Family
4 x PLL
(1)
FOSC<2:0>
Secondary Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source Option
for Other Modules
OSC1
OSC2
Sleep
HSPLL, ECPLL, INTPLL
HS, EC
T1OSC
CPU
Peripherals
IDLEN
Postscaler
MUX
MUX
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
OSCCON<6:4>
111
110
101
100
011
010
001
000
31 kHz
INTRC
Source
Internal
Oscillator
Block
WDT, PWRT, FSCM
8 MHz
Internal Oscillator
(INTOSC)
OSCCON<6:4>
Clock
Control
OSCCON<1:0>
Source
8 MHz
31 kHz (INTRC)
0
1
OSCTUNE<7>
and Two-Speed Start-up
Primary Oscillator
OSCTUNE<7>
Note 1: 8 MHz and 4 MHz are valid INTOSC postscaler settings for the PLL. Selecting other INTOSC postscaler
settings will operate the PLL outside of the specification.