Datasheet

2011 Microchip Technology Inc. DS39932D-page 347
PIC18F46J11 FAMILY
TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69
PIR1 PMPIF
(1)
ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72
PIE1
PMPIE
(1)
ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72
IPR1 PMPIP
(1)
ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF 72
PIE3
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE 72
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP 72
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 72
RCREGx EUSARTx Receive Register 72
TXSTAx CSRC
TX9 TXEN SYNC SENDB BRGH TRMT TX9D 72
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16 WUE ABDEN 73
SPBRGHx EUSARTx Baud Rate Generator Register High Byte 73
SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72
ODCON2
U2OD U1OD 74
Legend: — = unimplemented, read as0’. Shaded cells are not used for synchronous master reception.
Note 1: These pins are only available on 44-pin devices.