Datasheet
2011 Microchip Technology Inc. DS39932D-page 271
PIC18F46J11 FAMILY
19.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices include serial EEPROMs, shift registers,
display drivers and A/D Converters.
19.1 Master SSP (MSSP) Module
Overview
The MSSP module can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
2
C™)
- Full Master mode
- Slave mode (with general address call)
The I
2
C interface supports the following modes in
hardware:
•Master mode
• Multi-Master mode
• Slave mode with 5-bit and 7-bit address masking
(with address masking for both 10-bit and 7-bit
addressing)
All members of the PIC18F46J11 family have two
MSSP modules, designated as MSSP1 and MSSP2.
The modules operate independently:
• PIC18F4XJ11 devices – Both modules can be
configured for either I
2
C or SPI communication
• PIC18F2XJ11 devices:
- MSSP1 can be used for either I
2
C or SPI
communication
- MSSP2 can be used only for SPI
communication
All of the MSSP1 module-related SPI and I
2
C I/O
functions are hard-mapped to specific I/O pins.
For MSSP2 functions:
• SPI I/O functions (SDO2, SDI2, SCK2 and SS2
)
are all routed through the Peripheral Pin Select
(PPS) module.
These functions may be configured to use any of
the RPn remappable pins, as described in
Section 10.7 “Peripheral Pin Select (PPS)”.
•I
2
C functions (SCL2 and SDA2) have fixed pin
locations.
On all PIC18F46J11 family devices, the SPI DMA capa-
bility can only be used in conjunction with MSSP2. The
SPI DMA feature is described in Section 19.4 “SPI
DMA Module”.
Note: Throughout this section, generic
references to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names and module I/O
signals use the generic designator ‘x’ to
indicate the use of a numeral to distinguish
a particular module when required. Control
bit names are not individuated.