Datasheet
2011 Microchip Technology Inc. DS39932D-page 269
PIC18F46J11 FAMILY
18.5.8 OPERATION IN POWER-MANAGED
MODES
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCPx pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCPx module without change.
18.5.8.1 Operation with Fail-Safe
Clock Monitor (FSCM)
If the Fail-Safe Clock Monitor (FSCM) is enabled, a
clock failure will force the device into the
power-managed RC_RUN mode and the OSCFIF bit of
the PIR2 register will be set. The ECCPx will then be
clocked from the internal oscillator clock source, which
may have a different clock frequency than the primary
clock.
18.5.9 EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states.
This forces the ECCP module to reset to a state
compatible with previous, non-enhanced ECCP
modules used on other PIC18 and PIC16 devices.
TABLE 18-5: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 69
RCON IPEN
— — RI TO PD POR BOR 70
PIR1
PMPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 72
PIE1 PMPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 72
IPR1
PMPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 72
PIR2 OSCFIF CM2IF CM1IF — BCL1IF LVDIF TMR3IF CCP2IF 72
PIE2
OSCFIE CM2IE CM1IE — BCL1IE LVDIE TMR3IE CCP2IE 72
IPR2 OSCFIP CM2IP CM1IP — BCL1IP LVDIP TMR3IP CCP2IP 72
TRISC TRISC7 TRISC6 TRISC5 TRISC4
TRISC3 TRISC2 TRISC1 TRISC0 72
TMR1L Timer1 Register Low Byte 70
TMR1H Timer1 Register High Byte 70
TCLKCON
— — — T1RUN — — T3CCP2 T3CCP1 94
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
RD16 TMR1ON 70
TMR2 Timer2 Register 70
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 70
PR2 Timer2 Period Register 70
TMR3L Timer3 Register Low Byte 73
TMR3H Timer3 Register High Byte 73
T3CON
TMR3CS1
TMR3CS0 T3CKPS1 T3CKPS0 — T3SYNC RD16 TMR3ON 73
CCPR1L Capture/Compare/PWM Register 1 Low Byte 72
CCPR1H Capture/Compare/PWM Register 1 High Byte 72
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 72
ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 70
ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 72
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: These bits are only available on 44-pin devices.