Datasheet

 2011 Microchip Technology Inc. DS39932D-page 195
PIC18F46J11 FAMILY
TABLE 11-2: REGISTERS ASSOCIATED WITH PMP MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69
PIR1 PMPIF
(2)
ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 72
PIE1 PMPIE
(2)
ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 72
IPR1 PMPIP
(2)
ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 72
PMCONH
(2)
PMPEN — — ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 73
PMCONL
(2)
CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 73
PMADDRH
(1,2)
/ — CS1 Parallel Master Port Address High Byte 73
PMDOUT1H
(1,2)
Parallel Port Out Data High Byte (Buffer 1) 73
PMADDRL
(1,2)
/ Parallel Master Port Address Low Byte 73
PMDOUT1L
(1,2)
Parallel Port Out Data Low Byte (Buffer 0) 73
PMDOUT2H
(2)
Parallel Port Out Data High Byte (Buffer 3) 73
PMDOUT2L
(2)
Parallel Port Out Data Low Byte (Buffer 2) 73
PMDIN1H
(2)
Parallel Port In Data High Byte (Buffer 1) 73
PMDIN1L
(2)
Parallel Port In Data Low Byte (Buffer 0) 73
PMDIN2H
(2)
Parallel Port In Data High Byte (Buffer 3) 73
PMDIN2L
(2)
Parallel Port In Data Low Byte (Buffer 2) 73
PMMODEH
(2)
BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 73
PMMODEL
(2)
WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 73
PMEH
(2)
—PTEN14— — — — — —74
PMEL
(2)
PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 74
PMSTATH
(2)
IBF IBOV — — IB3F IB2F IB1F IB0F 74
PMSTATL
(2)
OBE OBUF — — OB3E OB2E OB1E OB0E 74
PADCFG1 — — — — — RTSECSEL1 RTSECSEL0 PMPTTL 74
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during PMP operation.
Note 1: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and
addresses, but have different functions determined by the module’s operating mode.
2: These bits and/or registers are only available in 44-pin devices.