Datasheet

 2011 Microchip Technology Inc. DS39932D-page 173
PIC18F46J11 FAMILY
REGISTER 11-2: PMCONL: PARALLEL PORT CONTROL REGISTER LOW BYTE (BANKED F5Eh)
(1)
R/W-0 R/W-0 R/W-0
(2)
U-0 R/W-0
(2)
R/W-0 R/W-0 R/W-0
CSF1 CSF0 ALP
— CS1P BEP WRSP RDSP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 CSF<1:0>: Chip Select Function bits
11 = Reserved
10 = Chip select function is enabled and PMCS acts as chip select (in Master mode). Up to 13 address
bits only can be generated.
01 = Reserved
00 = Chip select function is disabled (in Master mode). All 16 address bits can be generated.
bit 5 ALP: Address Latch Polarity bit
(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL
and PMALH)
bit 4 Unimplemented: Maintain as ‘0’
bit 3 CS1P: Chip Select Polarity bit
(2)
1 = Active-high (PMCS)
0 =Active-low (PMCS
)
bit 2 BEP: Byte Enable Polarity bit
1 = Byte enable active-high (PMBE)
0 = Byte enable active-low (PMBE
)
bit 1 WRSP: Write Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODEH<1:0> = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR
)
For Master Mode 1 (PMMODEH<1:0> = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB
)
bit 0 RDSP: Read Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODEH
<1:0> = 00,01,10):
1 = Read strobe active-high (PMRD)
0 = Read strobe active-low (PMRD
)
For Master Mode 1 (PMMODEH<1:0> = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD
/PMWR)
Note 1: This register is only available in 44-pin devices.
2: These bits have no effect when their corresponding pins are used as address lines.