Datasheet

PIC18F46J11 FAMILY
DS39932D-page 148  2011 Microchip Technology Inc.
10.6 PORTE, TRISE and LATE
Registers
Depending on the particular PIC18F46J11 family
device selected, PORTE is implemented in two
different ways.
For 44-pin devices, PORTE is a 3-bit wide port. Three
pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/
AN7/PMCS) are individually configurable as inputs or
outputs. These pins have Schmitt Trigger input buffers.
When selected as analog inputs, these pins will read as
‘0’s.
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
EXAMPLE 10-6: INITIALIZING PORTE
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by setting bit, REPU (PORTE<6>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
POR.
Note that the pull-ups can be used for any set of
features, similar to the pull-ups found on PORTB.
Note: PORTE is available only in 44-pin
devices.
Note: On a POR, RE<2:0> are configured as
analog inputs.
CLRF LATE ; Initialize LATE
; to clear output
; data latches
MOVLW 0xE0 ; Configure REx
MOVWF ANCON0 ; for digital inputs
MOVLW 0x03 ; Value used to
; initialize data
; direction
MOVWF TRISE ; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs