Datasheet
PIC18F46J11 FAMILY
DS39932D-page 146 2011 Microchip Technology Inc.
TABLE 10-9: PORTD I/O SUMMARY
Pin Function
TRIS
Setting
I/O
I/O
Type
Description
RD0/PMD0/
SCL2
RD0 1 I ST PORTD<0> data input.
0 O DIG LATD<0> data output.
PMD0 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
SCL2 1 II
2
C/
SMB
I
2
C™ clock input (MSSP2 module); input type depends on
module setting.
0 ODIGI
2
C™ clock output (MSSP2 module); takes priority over port
data.
RD1/PMD1/
SDA2
RD1 1 I ST PORTD<1> data input.
0 O DIG LATD<1> data output.
PMD1 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
SDA2 1 II
2
C/
SMB
I
2
C data input (MSSP2 module); input type depends on
module setting.
0 ODIGI
2
C data output (MSSP2 module); takes priority over port
data.
RD2/PMD2/
RP19
RD2 1 I ST PORTD<2> data input.
0 O DIG LATD<2> data output.
PMD2 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
RP19 1 I ST Remappable peripheral pin 19 input.
0 O DIG Remappable peripheral pin 19 output.
RD3/PMD3/
RP20
RD3 1 I DIG PORTD<3> data input.
0 O DIG LATD<3> data output.
PMD3 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
RP20 1 I ST Remappable peripheral pin 20 input.
0 O DIG Remappable peripheral pin 20 output.
RD4/PMD4/
RP21
RD4 1 I ST PORTD<4> data input.
0 O DIG LATD<4> data output.
PMD4 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
RP21 1 I ST Remappable peripheral pin 21 input.
0 O DIG Remappable peripheral pin 21 output.
RD5/PMD5/
RP22
RD5 1 I ST PORTD<5> data input.
0 O DIG LATD<5> data output.
PMD5 1 I ST/TTL Parallel Master Port data in.
0 O DIG Parallel Master Port data out.
RP22 1 I ST Remappable peripheral pin 22 input.
0 O DIG Remappable peripheral pin 22 output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I
2
C/SMB = I
2
C/SMBus
input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).