Datasheet
PIC18F46J11 FAMILY
DS39932D-page 100 2011 Microchip Technology Inc.
6.6.1 INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under
proper conditions, instructions that use the Access
Bank, that is, most bit and byte-oriented instructions,
can invoke a form of Indexed Addressing using an
offset specified in the instruction. This special address-
ing mode is known as Indexed Addressing with Literal
Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
and
• The file address argument is less than or equal to
5Fh.
Under these conditions, the file address of the instruc-
tion is not interpreted as the lower byte of an address
(used with the BSR in Direct Addressing) or as an 8-bit
address in the Access Bank. Instead, the value is inter-
preted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
6.6.2 INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all byte
and bit-oriented instructions, or almost one-half of the
standard PIC18 instruction set. Instructions that only
use Inherent or Literal Addressing modes are
unaffected.
Additionally, byte and bit-oriented instructions are not
affected if they do not use the Access Bank (Access
RAM bit is ‘1’) or include a file address of 60h or above.
Instructions meeting these criteria will continue to
execute as before. A comparison of the different possi-
ble addressing modes when the extended instruction set
is enabled is provided in Figure 6-9.
Those who desire to use byte or bit-oriented instruc-
tions in the Indexed Literal Offset mode should note the
changes to assembler syntax for this mode. This is
described in more detail in Section 27.2.1 “Extended
Instruction Syntax”.