Datasheet

© 2009 Microchip Technology Inc. DS39637D-page 85
PIC18F2480/2580/4480/4580
SPBRGH EUSART Baud Rate Generator High Byte 0000 0000 57, 236
SPBRG EUSART Baud Rate Generator 0000 0000 57, 236
RCREG EUSART Receive Register 0000 0000 57, 244
TXREG EUSART Transmit Register 0000 0000 57, 241
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 57, 243
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 57, 243
EEADR EEPROM Address Register 0000 0000 57, 111
EEDATA EEPROM Data Register 0000 0000 57, 111
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 57, 111
EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD xx-0 x000 57, 111
IPR3
Mode 0
IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP 1111 1111 57, 132
IPR3
Mode 1, 2
IRXIP WAKIP ERRIP TXBnIP
TXB1IP
(8)
TXB0IP
(8)
RXBnIP FIFOWMIP 1111 1111 57, 132
PIR3
Mode 0
IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF 0000 0000 57, 126
PIR3
Mode 1, 2
IRXIF WAKIF ERRIF TXBnIF
TXB1IF
(8)
TXB0IF
(8)
RXBnIF FIFOWMIF 0000 0000 57, 126
PIE3
Mode 0
IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE 0000 0000 57, 129
PIE3
Mode 1, 2
IRXIE WAKIE ERRIE TXBnIE
TXB1IE
(8)
TXB0IE
(8)
RXBnIE FIFOMWIE 0000 0000 57, 129
IPR2 OSCFIP CMIP
(9)
— EEIP BCLIP HLVDIP TMR3IP ECCP1IP
(9)
11-1 1111 57, 131
PIR2 OSCFIF CMIF
(9)
— EEIF BCLIF HLVDIF TMR3IF ECCP1IF
(9)
00-0 0000 58, 125
PIE2 OSCFIE CMIE
(9)
— EEIE BCLIE HLVDIE TMR3IE ECCP1IE
(9)
00-0 0000 58, 128
IPR1 PSPIP
(3)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 58, 130
PIR1 PSPIF
(3)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 58, 124
PIE1 PSPIE
(3)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 58, 127
OSCTUNE INTSRC PLLEN
(4)
— TUN4 TUN3 TUN2 TUN1 TUN0 0q-0 0000 33, 58
TRISE
(3)
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 58, 146
TRISD
(3)
PORTD Data Direction Register 1111 1111 58, 143
TRISC PORTC Data Direction Register 1111 1111 58, 141
TRISB PORTB Data Direction Register 1111 1111 58, 138
TRISA TRISA7
(6)
TRISA6
(6)
PORTA Data Direction Register 1111 1111 58, 135
LATE
(3)
— — — — —LATE2LATE1LATE0---- -xxx 58, 146
LATD
(3)
LATD Output Latch Register xxxx xxxx 58, 143
LATC LATC Output Latch Register xxxx xxxx 58, 141
LATB LATB Output Latch Register xxxx xxxx 58, 138
LATA LATA7
(6)
LATA6
(6)
LATA Output Latch Register xxxx xxxx 58, 135
TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.