Datasheet

PIC18F2480/2580/4480/4580
DS39637D-page 366 © 2009 Microchip Technology Inc.
25.5.2 DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits internal and external writes to data
EEPROM. The CPU can continue to read and write
data EEPROM regardless of the protection bit settings.
25.5.3 CONFIGURATION REGISTER
PROTECTION
The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
25.6 ID Locations
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRD and TBLWT instructions
or during program/verify. The ID locations can be read
when the device is code-protected.
25.7 In-Circuit Serial Programming
PIC18F2480/2580/4480/4580 microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock and data
and three other lines for power, ground and the
programming voltage. This allows customers to manu-
facture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
25.8 In-Circuit Debugger
When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB
®
IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use. Table 25-4 shows which resources are
required by the background debugger.
TABLE 25-4: DEBUGGER RESOURCES
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP/RE3, VDD,
V
SS, RB7 and RB6. This will interface to the In-Circuit
debugger module available from Microchip or one of
the third party development tool companies.
25.9 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply ICSP
Programming (formerly known as Low-Voltage ICSP
Programming or LVP). When Single-Supply Program-
ming is enabled, the microcontroller can be
programmed without requiring high voltage being
applied to the MCLR
/VPP/RE3 pin, but the RB5/KBI1/
PGM pin is then dedicated to controlling Program mode
entry and is not available as a general purpose I/O pin.
While programming using Single-Supply Program-
ming, V
DD is applied to the MCLR/VPP/RE3 pin as in
normal execution mode. To enter Programming mode,
VDD is applied to the PGM pin.
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RB5/KBI1/PGM then
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (V
IHH applied to the MCLR/
V
PP/RE3 pin). Once LVP has been disabled, only the
standard high-voltage programming is available and
must be used to program the device.
Memory that is not code-protected can be erased using
either a block erase, or erased row by row, then written
at any specified V
DD. If code-protected memory is to be
erased, a block erase is required. If a block erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with V
DD of 4.5V to 5.5V.
I/O pins: RB6, RB7
Stack: 2 levels
Note: Memory resources listed in MPLAB
®
IDE.
Note 1: High-voltage programming is always avail-
able, regardless of the state of the LVP bit,
by applying VIHH to the MCLR pin.
2: While in Low-Voltage ICSP Programming
mode, the RB5 pin can no longer be used
as a general purpose I/O pin and should
be held low during normal operation.
3: When using Low-Voltage ICSP Program-
ming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.
4: If the device Master Clear is disabled,
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low-Voltage Programming
(CONFIG4l<2> = 0); or
b) make certain that RB5/PGM is held
low during entry into ICSP.