Datasheet

PIC18F2450/4450
© 2008 Microchip Technology Inc. DS39760D-page 81
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3 UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT time-out Reset
during normal operation, the user can check the
WRERR bit and rewrite the location(s) as needed.
6.5.4 PROTECTION AGAINST SPURIOUS
WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 18.0 “Special Features of the
CPU” for more detail.
6.6 Flash Program Operation During
Code Protection
See Section 18.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
PROGRAM_MEMORY
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
DECFSZ COUNTER1
BRA WRITE_BUFFER_BACK
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
TBLPTRU
— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 49
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 49
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 49
TABLAT Program Memory Table Latch 49
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
EECON2 Data Memory Control Register 2 (not a physical register) 51
EECON1
—CFGS— FREE WRERR WREN WR —51
IPR2 OSCFIP — USBIP — — HLVDIP — —51
PIR2 OSCFIF
— USBIF — — HLVDIF — —51
PIE2 OSCFIE
— USBIE — — HLVDIE — —51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access.