Datasheet

PIC18F2450/4450
© 2008 Microchip Technology Inc. DS39760D-page 65
PORTC RC7 RC6 RC5
(6)
RC4
(6)
— RC2 RC1 RC0 xxxx -xxx 51, 106
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 51, 100
PORTA
—RA6
(4)
RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 51, 100
UEP15
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
UEP14
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
UEP13
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
UEP12
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
UEP11
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
UEP10
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
UEP9
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
UEP8
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
UEP7
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
UEP6
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
UEP5
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
UEP4
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
UEP3
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
UEP2
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
UEP1
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
UEP0
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
UCFG UTEYE UOEMON
— UPUEN UTRDIS FSEN PPB1 PPB0 00-0 0000 52, 132
UADDR
— ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 52, 136
UCON
— PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- 52, 130
USTAT
— ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx- 52, 134
UEIE BTSEE
— — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 52, 148
UEIR BTSEF
— — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 52, 147
UIE
— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 52, 146
UIR
— SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 52, 144
UFRMH
— — — — — FRM10 FRM9 FRM8 ---- -xxx 52, 136
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 52, 136
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).