Datasheet

PIC18F2450/4450
DS39760D-page 64 © 2008 Microchip Technology Inc.
OSCCON IDLEN — — —OSTS— SCS1 SCS0 0--- q-00 50, 31
HLVDCON VDIRMAG
— IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 50, 185
WDTCON
— — — — — — —SWDTEN--- ---0 50, 204
RCON IPEN SBOREN
(2)
—RITO PD POR BOR 0q-1 11q0 50, 42
TMR1H Timer1 Register High Byte xxxx xxxx 50, 120
TMR1L Timer1 Register Low Byte xxxx xxxx 50, 120
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 50, 115
TMR2 Timer2 Register 0000 0000 50, 122
PR2 Timer2 Period Register 1111 1111 50, 122
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 121
ADRESH A/D Result Register High Byte xxxx xxxx 50, 184
ADRESL A/D Result Register Low Byte xxxx xxxx 50, 184
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 50, 175
ADCON1
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 qqqq 50, 176
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 50, 177
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 50, 124
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 50, 124
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 50, 123,
BAUDCON ABDOVF RCIDL
— SCKP BRG16 — WUE ABDEN 01-0 0-00 51, 156,
SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 50, 157
SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 50, 157
RCREG EUSART Receive Register 0000 0000 50, 165
TXREG EUSART Transmit Register 0000 0000 51, 163
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 51, 154
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 51, 155
EECON2 Data Memory Control Register 2 (not a physical register) 0000 0000 51, 74
EECON1
—CFGS— FREE WRERR WREN WR — -x-0 x00- 51, 75
IPR2 OSCFIP
— USBIP — —HLVDIP— — 1-1- -1-- 51, 95
PIR2 OSCFIF
—USBIF— —HLVDIF— — 0-0- -0-- 51, 91
PIE2 OSCFIE
— USBIE — —HLVDIE— — 0-0- -0-- 51, 93
IPR1
— ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 51, 94
PIR1
— ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 51, 90
PIE1
— ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 51, 92
TRISE
(3)
— — — — — TRISE2 TRISE1 TRISE0 ---- -111 51, 110
TRISD
(3)
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 51, 108
TRISC TRISC7 TRISC6
— — — TRISC2 TRISC1 TRISC0 11-- -111 51, 106
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 51, 103
TRISA
— TRISA6
(4)
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 51, 100
LATE
(3)
— — — — — LATE2 LATE1 LATE0 ---- -xxx 51, 110
LATD
(3)
LATD7LATD6LATD5LATD4LATD3LATD2LATD1LATD0xxxx xxxx 51, 108
LATC LATC7 LATC6
— — — LATC2 LATC1 LATC0 xx-- -xxx 51, 106
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 51, 103
LATA
—LATA6
(4)
LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 -xxx xxxx 51, 100
PORTE
— — — —RE3
(5)
RE2
(3)
RE1
(3)
RE0
(3)
---- x000 51, 109
PORTD
(3)
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 51, 108
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).