Datasheet

PIC18F2450/4450
© 2008 Microchip Technology Inc. DS39760D-page 51
TXREG 2450 4450 0000 0000 0000 0000 uuuu uuuu
TXSTA 2450 4450 0000 0010 0000 0010 uuuu uuuu
RCSTA 2450 4450 0000 000x 0000 000x uuuu uuuu
EECON2 2450 4450 0000 0000 0000 0000 0000 0000
EECON1 2450 4450 -x-0 x00- -u-0 u00- -u-0 u00-
IPIR2 2450 4450 1-1- -1-- 1-1- -1-- u-u- -u--
PIR2 2450 4450 0-0- -0-- 0-0- -0-- u-u- -u--
(2)
PIE2 2450 4450 0-0- -0-- 0-0- -0-- u-u- -u--
IPR1
2450 4450 -111 -111 -111 -111 -uuu -uuu
PIR1 2450 4450 -000 -000 -000 -000 -uuu -uuu
(2)
PIE1 2450 4450 -000 -000 -000 -000 -uuu -uuu
TRISE
2450 4450 ---- -111 ---- -111 ---- -uuu
TRISD 2450 4450 1111 1111 1111 1111 uuuu uuuu
TRISC 2450 4450 11-- -111 11-- -111 uu-- -uuu
TRISB 2450 4450 1111 1111 1111 1111 uuuu uuuu
TRISA
(5)
2450 4450 -111 1111
(5)
-111 1111
(5)
-uuu uuuu
(5)
LATE 2450 4450 ---- -xxx ---- -uuu ---- -uuu
LATD
2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 2450 4450 xx-- -xxx uu-- -uuu uu-- -uuu
LATB 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
LATA
(5)
2450 4450 -xxx xxxx
(5)
-uuu uuuu
(5)
-uuu uuuu
(5)
PORTE 2450 4450 ---- x000 ---- x000 ---- uuuu
PORTD 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 2450 4450 xxxx -xxx uuuu -uuu uuuu -uuu
PORTB 2450 4450 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA
(5)
2450 4450 -x0x 0000
(5)
-u0u 0000
(5)
-uuu uuuu
(5)
UEP15 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP14 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP13 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP12 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP11 2450 4450 ---0 0000 ---0 0000 ---u uuuu
UEP10 2450 4450 ---0 0000 ---0 0000 ---u uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.