Datasheet

PIC18F2450/4450
DS39760D-page 36 © 2008 Microchip Technology Inc.
3.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. When using the INTRC source, this mode
provides the best power conservation of all the Run
modes while still executing code. It works well for user
applications which are not highly timing sensitive or do
not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
(INTRC), there are no distinguishable differences
between the PRI_RUN and RC_RUN modes during
execution. However, a clock switch delay will occur dur-
ing entry to and exit from RC_RUN mode. Therefore, if
the primary clock source is the internal oscillator, the
use of RC_RUN mode is not recommended.
This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
the INTRC (see Figure 3-3), the primary oscillator is
shut down and the OSTS bit is cleared.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 3-4). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE
FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q4Q3Q2
OSC1
Peripheral
Program
Q1
INTRC
Q1
Counter
Clock
CPU
Clock
PC + 2PC
123 n-1n
Clock Transition
(1)
Q4Q3Q2 Q1 Q3Q2
PC + 4
Note 1: Clock transition typically occurs within 2-4 T
OSC.
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
INTRC
PLL Clock
Q1
PC + 4
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 2
Clock
Counter
Q2
Q2
Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 T
OSC.
SCS1:SCS0 bits Changed
TPLL
(1)
12 n-1n
Clock
(2)
OSTS bit Set
Transition
TOST
(1)