Datasheet

PIC18F2450/4450
© 2008 Microchip Technology Inc. DS39760D-page 35
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 3-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up; the Timer1
oscillator continues to run.
FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q4Q3Q2
OSC1
Peripheral
Program
Q1
T1OSI
Q1
Counter
Clock
CPU
Clock
PC + 2PC
123
n-1 n
Clock Transition
(1)
Q4Q3Q2 Q1 Q3Q2
PC + 4
Note 1: Clock transition typically occurs within 2-4 T
OSC.
Q1 Q3 Q4
OSC1
Peripheral
Program
PC
T1OSI
PLL Clock
Q1
PC + 4
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 2
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 T
OSC.
SCS1:SCS0 bits Changed
TPLL
(1)
12 n-1n
Clock
(2)
OSTS bit Set
Transition
TOST
(1)