Datasheet

PIC18F2450/4450
DS39760D-page 288 © 2008 Microchip Technology Inc.
FIGURE 21-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 21-8: BROWN-OUT RESET TIMING
TABLE 21-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 — — μs
31 TWDT Watchdog Timer Time-out Period
(no postscaler)
— 4.00 4.6 ms
32 TOST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 TPWRT Power-up Timer Period — 65.5 75 ms
34 T
IOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—2—μs
35 TBOR Brown-out Reset Pulse Width 200 — — μsVDD ≤ BVDD (see D005)
36 TIRVST Time for Internal Reference
Voltage to become Stable
—2050 μs
37 T
LVD Low-Voltage Detect Pulse Width 200 — — μsVDD ≤ VLVD
38 TCSD CPU Start-up Time 5 — 10 μs
39 TIOBST Time for INTRC to Stabilize — 1 — ms
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 21-4 for load conditions.
VDD
BVDD
35
VBGAP = 1.2V
V
IRVST
Enable Internal
Internal Reference
36
Reference Voltage
Voltage Stable