Datasheet

PIC18F2450/4450
© 2008 Microchip Technology Inc. DS39760D-page 285
21.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 21-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
TABLE 21-6: EXTERNAL CLOCK TIMING REQUIREMENTS
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3
3
4
4
Param.
No.
Symbol Characteristic Min Max Units Conditions
1A F
OSC External CLKI Frequency
(1)
Oscillator Frequency
(1)
DC 48 MHz EC, ECIO Oscillator modes
0.2 1 MHz XT, XTPLL Oscillator modes
4 25 MHz HS Oscillator mode
4 25 MHz HSPLL Oscillator mode
1T
OSC External CLKI Period
(1)
Oscillator Period
(1)
20.8 — ns EC, ECIO Oscillator modes
1,000 5,000 ns XT Oscillator mode
40
40
250
250
ns
ns
HS Oscillator mode
HSPLL Oscillator mode
2T
CY Instruction Cycle Time
(1)
83.3 — ns TCY = 4/FOSC
3 TosL,
To sH
External Clock in (OSC1)
High or Low Time
30 — ns XT Oscillator mode
10 — ns HS Oscillator mode
4TosR,
To sF
External Clock in (OSC1)
Rise or Fall Time
— 20 ns XT Oscillator mode
— 7.5 ns HS Oscillator mode
Note 1: Instruction cycle period (T
CY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.