Datasheet

PIC18F2450/4450
DS39760D-page 208 © 2008 Microchip Technology Inc.
18.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
®
microcontrollers.
The user program memory is divided into three blocks.
One of these is a boot block of 1 or 2 Kbytes. The
remainder of the memory is divided into two blocks on
binary boundaries.
Each of the three blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPx)
• Write-Protect bit (WRTx)
• External Block Table Read bit (EBTRx)
Figure 18-5 shows the program memory organization
for 24 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 18-3.
FIGURE 18-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2450/4450
TABLE 18-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L — — — — — —CP1CP0
300009h CONFIG5H
—CPB— — — — — —
30000Ah CONFIG6L
— — — — — — WRT1 WRT0
30000Bh CONFIG6H
—WRTBWRTC— — — — —
30000Ch CONFIG7L
— — — — — — EBTR1 EBTR0
30000Dh CONFIG7H — EBTRB — — — — — —
Legend: Shaded cells are unimplemented.
MEMORY SIZE/DEVICE
Block Code Protection
Controlled By:
16 Kbytes
(PIC18F2450/4450)
Address
Range
Boot Block
000000h
0007FFh
000FFFh
CPB, WRTB, EBTRB
Block 0
001000h
001FFFh
CP0, WRT0, EBTR0
Block 1
002000h
003FFFh
CP1, WRT1, EBTR1
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
1FFFFFh
(Unimplemented Memory Space)