Datasheet

PIC18F2450/4450
DS39760D-page 170 © 2008 Microchip Technology Inc.
FIGURE 15-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 15-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 51
PIE1
— ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 51
IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP 51
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
TXREG EUSART Transmit Register 51
TXSTA CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D 51
BAUDCON ABDOVF RCIDL —SCKPBRG16— WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register High Byte 50
SPBRG EUSART Baud Rate Generator Register Low Byte 50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0
bit 1
bit 2
bit 6 bit 7
TXEN bit