Datasheet

PIC18F2450/4450
DS39760D-page 166 © 2008 Microchip Technology Inc.
FIGURE 15-7: ASYNCHRONOUS RECEPTION
TABLE 15-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 51
PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 51
IPR1
— ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP 51
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
RCREG EUSART Receive Register 50
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register High Byte 50
SPBRG EUSART Baud Rate Generator Register Low Byte 50
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Start
bit
bit 7/8
bit 1bit 0 bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RX (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun Error) bit to be set.