Datasheet

PIC18F2450/4450
DS39760D-page 164 © 2008 Microchip Technology Inc.
FIGURE 15-4: ASYNCHRONOUS TRANSMISSION
FIGURE 15-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 15-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1
— ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 51
PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 51
IPR1
— ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP 51
RCSTA
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
TXREG EUSART Transmit Register 51
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51
BAUDCON
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register High Byte 50
SPBRG EUSART Baud Rate Generator Register Low Byte 50
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Word 1
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG
BRG Output
(Shift Clock)
TX
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
(pin)
Word 1
Stop bit
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Stop bit
Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0 bit 1
bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
(pin)
Start bit