Datasheet

PIC18F2450/4450
DS39760D-page 126 © 2008 Microchip Technology Inc.
TABLE 13-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
RCON IPEN
SBOREN
(1)
— RI TO PD POR BOR 50
PIR1
— ADIF RCIF TXIF —CCP1IFTMR2IF TMR1IF 51
PIE1 — ADIE RCIE TXIE —CCP1IETMR2IE TMR1IE 51
IPR1 — ADIP RCIP TXIP —CCP1IPTMR2IP TMR1IP 51
TRISC TRISC7 TRISC6
— — — TRISC2 TRISC1 TRISC0 51
TMR1L Timer1 Register Low Byte 50
TMR1H Timer1 Register High Byte 50
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 50
CCPR1L Capture/Compare/PWM Register 1 Low Byte 50
CCPR1H Capture/Compare/PWM Register 1 High Byte 50
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by capture/compare and Timer1.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.